Patents by Inventor Masashi Tsubuku

Masashi Tsubuku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11980048
    Abstract: According to one embodiment, a display device comprises a first area including a pixel and a second area different from the first area, wherein the pixel comprises a pixel electrode, an organic material layer including a light-emitting layer, a common electrode, a first insulating layer, a second insulating layer having a refractive index lower than that of the first insulating layer, and a third insulating layer, the second area is an area not overlapping the light-emitting layer in plan view, the second area is a transparent area, and the second area comprises the first insulating layer provided therein, the second area does not comprise the second insulating layer.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: May 7, 2024
    Assignee: Japan Display Inc.
    Inventors: Hayata Aoki, Masashi Tsubuku, Toshinari Sasaki
  • Patent number: 11978742
    Abstract: A metal oxide film including a crystal part and having highly stable physical properties is provided. The size of the crystal part is less than or equal to 10 nm, which allows the observation of circumferentially arranged spots in a nanobeam electron diffraction pattern of the cross section of the metal oxide film when the measurement area is greater than or equal to 5 nm? and less than or equal to 10 nm?.
    Type: Grant
    Filed: April 20, 2023
    Date of Patent: May 7, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masahiro Takahashi, Takuya Hirohashi, Masashi Tsubuku, Noritaka Ishihara, Masashi Oota
  • Patent number: 11973161
    Abstract: A photo sensor circuit includes: a photo transistor; a first switching transistor; a second switching transistor; and a capacitance element. The photo transistor includes: a gate connected to a first wiring; a source connected to a second wiring; and a drain. The first switching transistor includes: a gate connected to a third wiring; a source connected to a fourth wiring; and a drain connected to the drain of the photo transistor. The capacitance element includes: a first terminal connected to the drain of the photo transistor; and a second terminal connected to the source of the first switching transistor. The second switching transistor includes: a gate connected to a gate line; a source connected to a signal line; and a drain connected to the first terminal of the capacitance element. The photo transistor, first switching transistor, and second transistor each include an oxide semiconductor layer as a channel layer.
    Type: Grant
    Filed: December 30, 2022
    Date of Patent: April 30, 2024
    Assignee: JAPAN DISPLAY INC.
    Inventors: Masashi Tsubuku, Takanori Tsunashima, Marina Mochizuki
  • Patent number: 11967505
    Abstract: A method for manufacturing a sputtering target with which an oxide semiconductor film with a small amount of defects can be formed is provided. Alternatively, an oxide semiconductor film with a small amount of defects is formed. A method for manufacturing a sputtering target is provided, which includes the steps of: forming a polycrystalline In-M-Zn oxide (M represents a metal chosen among aluminum, titanium, gallium, yttrium, zirconium, lanthanum, cesium, neodymium, and hafnium) powder by mixing, sintering, and grinding indium oxide, an oxide of the metal, and zinc oxide; forming a mixture by mixing the polycrystalline In-M-Zn oxide powder and a zinc oxide powder; forming a compact by compacting the mixture; and sintering the compact.
    Type: Grant
    Filed: April 21, 2023
    Date of Patent: April 23, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masashi Tsubuku, Masashi Oota, Yoichi Kurosawa, Noritaka Ishihara
  • Publication number: 20240113227
    Abstract: A method for manufacturing semiconductor device according to an embodiment includes: forming an oxide semiconductor layer above a substrate; forming a gate insulating layer above the oxide semiconductor layer; forming a metal oxide layer containing aluminum as a main component above the gate insulating layer; performing a heat treatment in a state where the metal oxide layer is formed above the gate insulating layer; removing the metal oxide layer after the heat treatment; and forming a gate electrode above the gate insulating layer.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 4, 2024
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Akihiro HANADA, Takaya TAMARU
  • Publication number: 20240113228
    Abstract: A semiconductor device according to an embodiment includes: an oxide insulating layer; an oxide semiconductor layer; a gate electrode; a gate insulating layer; and a first insulating layer, wherein the semiconductor device is divided into a first to a third regions, a thickness of the gate insulating layer in the first region is 200 nm or more, the gate electrode contacts the first insulating layer in the first region, the oxide semiconductor layer contacts the first insulating layer in the second region, an amount of impurities contained in the oxide semiconductor layer in the second region is greater than an amount of impurities contained in the oxide semiconductor layer in the first region, and an amount of impurities contained in the oxide insulating layer in the third region is greater than an amount of impurities contained in the oxide insulating layer in the second region.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 4, 2024
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Akihiro HANADA, Takaya TAMARU
  • Publication number: 20240105733
    Abstract: It is an object to manufacture a highly reliable display device using a thin film transistor having favorable electric characteristics and high reliability as a switching element. In a bottom gate thin film transistor including an amorphous oxide semiconductor, an oxide conductive layer having a crystal region is formed between an oxide semiconductor layer which has been dehydrated or dehydrogenated by heat treatment and each of a source electrode layer and a drain electrode layer which are formed using a metal material. Accordingly, contact resistance between the oxide semiconductor layer and each of the source electrode layer and the drain electrode layer can be reduced; thus, a thin film transistor having favorable electric characteristics and a highly reliable display device using the thin film transistor can be provided.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 28, 2024
    Inventors: Shunpei YAMAZAKI, Toshinari SASAKI, Junichiro SAKATA, Masashi TSUBUKU
  • Publication number: 20240105819
    Abstract: A method for manufacturing a semiconductor device includes depositing a first metal oxide film with aluminum as a major component on a substrate, depositing an amorphous oxide semiconductor film on the first metal oxide film under an oxygen partial pressure of 3% to 5%, processing the oxide semiconductor film into a patterned oxide semiconductor layer, crystallizing the oxide semiconductor layer by performing a first heat treatment on the patterned oxide semiconductor layer, processing the first metal oxide film using the crystallized oxide semiconductor layer as a mask, depositing a gate insulating film on the oxide semiconductor layer, and forming a gate electrode on the gate insulating film, wherein a thickness of the oxide semiconductor film is more than 10 nm and 30 nm or less.
    Type: Application
    Filed: September 26, 2023
    Publication date: March 28, 2024
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Takaya TAMARU
  • Publication number: 20240097043
    Abstract: A semiconductor device according to an embodiment of the present invention includes an oxide insulating layer, an oxide semiconductor layer, a gate insulating layer, a gate electrode, and a protective insulating layer. The gate insulating layer includes a first region overlapping the gate electrode and a second region not overlapping the gate electrode. The second region is in contact with the protective insulating layer. The oxide insulating layer includes a third region overlapping the gate electrode and a fourth region not overlapping the gate electrode and the oxide semiconductor layer. The fourth region is in contact with the gate insulating layer. The oxide semiconductor layer includes a channel region, a source region, and a drain region. Each of the source region, the drain region, and the second region contains an impurity. A hydrogen concentration of the second region is greater than a hydrogen concentration of the first region.
    Type: Application
    Filed: August 28, 2023
    Publication date: March 21, 2024
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Takay TAMARU
  • Patent number: 11935944
    Abstract: The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.
    Type: Grant
    Filed: September 2, 2022
    Date of Patent: March 19, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Shinya Sasagawa, Motomu Kurata, Masashi Tsubuku
  • Patent number: 11935965
    Abstract: A display device including a pixel having a memory. The pixel includes at least a display element, a capacitor, an inverter, and a switch. The switch is controlled with a signal held in the capacitor and a signal output from the inverter so that voltage is supplied to the display element. The inverter and the switch can be constituted by transistors with the same polarity. A semiconductor layer included in the pixel may be formed using a light-transmitting material. Moreover, a gate electrode, a drain electrode, and a capacitor electrode may be formed using a light-transmitting conductive layer. The pixel is formed using a light-transmitting material in such a manner, whereby the display device can be a transmissive display device while including a pixel having a memory.
    Type: Grant
    Filed: April 20, 2023
    Date of Patent: March 19, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Kengo Akimoto, Masashi Tsubuku, Toshinari Sasaki
  • Publication number: 20240088302
    Abstract: A semiconductor device according to an embodiment includes: a substrate; a metal oxide layer arranged above the substrate and having aluminum as the main component of the metal oxide layer; an oxide semiconductor layer arranged above the metal oxide layer; a gate electrode facing the oxide semiconductor layer; and a gate insulating layer between the oxide semiconductor layer and the gate electrode, wherein a thickness of the metal oxide layer is 1 nm or more and 4 nm or less.
    Type: Application
    Filed: September 12, 2023
    Publication date: March 14, 2024
    Applicant: Japan Display Inc.
    Inventors: Takaya TAMARU, Masashi TSUBUKU, Hajime WATAKABE, Toshinari SASAKI
  • Patent number: 11927859
    Abstract: A display device comprising a transistor and a display element over the transistor, wherein the transistor includes a gate electrode on an insulating surface, a gate insulating layer on the gate electrode, and source/drain electrodes on the oxide semiconductor layer and the gate insulating layer, each including a first conductive layer containing nitrogen and a second conductive layer on the first conductive layer, and an insulating layer contains oxygen on the oxide semiconductor layer and the source/drain electrodes.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: March 12, 2024
    Assignee: Japan Display Inc.
    Inventors: Masashi Tsubuku, Takeshi Sakai, Tatsuya Toda
  • Patent number: 11923206
    Abstract: An object is to provide a display device with excellent display characteristics, where a pixel circuit and a driver circuit provided over one substrate are formed using transistors which have different structures corresponding to characteristics of the respective circuits. The driver circuit portion includes a driver circuit transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using a metal film, and a channel layer is formed using an oxide semiconductor. The pixel portion includes a pixel transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using an oxide conductor, and a semiconductor layer is formed using an oxide semiconductor. The pixel transistor is formed using a light-transmitting material, and thus, a display device with higher aperture ratio can be manufactured.
    Type: Grant
    Filed: November 18, 2022
    Date of Patent: March 5, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata, Masashi Tsubuku, Kengo Akimoto, Miyuki Hosoba, Masayuki Sakakura, Yoshiaki Oikawa
  • Publication number: 20240057413
    Abstract: A display device includes a display panel including a display portion having a plurality of pixels; and a sensor element disposed on a rear side of the display portion. The display portion has a first region overlapping the sensor element and a second region other than the first region in a plan view. Each of the plurality of pixels has a semiconductor device including a channel portion and a conductive portion made of an oxide semiconductor having a polycrystalline structure. Each of the plurality of pixels in the first region is connected by a first signal line comprising the same layer as the conductive portion, and each of the plurality of pixels in the second region is connected by a second signal line comprising a metal layer connected to the conductive portion.
    Type: Application
    Filed: August 4, 2023
    Publication date: February 15, 2024
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Takaya TAMARU
  • Patent number: 11901465
    Abstract: The optical sensor includes a substrate, a first transistor for functioning as a light-receiving element and a second transistor for writing/reading in a pixel region provided on the substrate. The first transistor is formed by a transistor using polycrystalline silicon, the second transistor is formed by a transistor using an oxide semiconductor. A light-shielding layer is provided on the back side of the oxide semiconductor of the second transistor. Thus, it is possible to irradiate light to the optical sensor fora long time, and in addition to increasing the amount of light received by the first transistor, it is possible to suppress variations in the characteristics of the second transistor.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: February 13, 2024
    Assignee: Japan Display Inc.
    Inventor: Masashi Tsubuku
  • Publication number: 20240038899
    Abstract: It is an object to provide a highly reliable thin film transistor with stable electric characteristics, which includes an oxide semiconductor film. The channel length of the thin film transistor including the oxide semiconductor film is in the range of 1.5 ?m to 100 ?m inclusive, preferably 3 ?m to 10 ?m inclusive; when the amount of change in threshold voltage is less than or equal to 3 V, preferably less than or equal to 1.5 V in an operation temperature range of room temperature to 180° C. inclusive or ?25° C. to 150° C. inclusive, a semiconductor device with stable electric characteristics can be manufactured. In particular, in a display device which is an embodiment of the semiconductor device, display unevenness due to variation in threshold voltage can be reduced.
    Type: Application
    Filed: October 5, 2023
    Publication date: February 1, 2024
    Inventors: Shunpei YAMAZAKI, Masashi TSUBUKU, Hiromichi GODO
  • Publication number: 20240021668
    Abstract: A semiconductor device includes an oxide semiconductor layer having a polycrystalline structure on an insulating surface, a gate electrode over the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate electrode. The oxide semiconductor layer includes a first region having a first crystal structure overlapping the gate electrode and a second region having a second crystal structure not overlapping the gate electrode. An electrical conductivity of the second region is larger than an electrical conductivity of the first region. The second crystal structure is identical to the first crystal structure.
    Type: Application
    Filed: June 15, 2023
    Publication date: January 18, 2024
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Takaya TAMARU
  • Publication number: 20240021695
    Abstract: A semiconductor device includes a oxide semiconductor layer provided on an insulating surface and having a channel area, a source area and a drain area sandwiching the channel area, a gate electrode opposite the channel area, and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode, wherein the gate electrode is an oxide conductive layer having the same composition as the oxide semiconductor layer, and the oxide conductive layer includes the same impurity element as the source area and the drain area.
    Type: Application
    Filed: July 3, 2023
    Publication date: January 18, 2024
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Takaya TAMARU
  • Publication number: 20240014222
    Abstract: The semiconductor device includes a driver circuit portion including a driver circuit and a pixel portion including a pixel. The pixel includes a gate electrode layer having a light-transmitting property, a gate insulating layer, a source electrode layer and a drain electrode layer each having a light-transmitting property provided over the gate insulating layer, an oxide semiconductor layer covering top surfaces and side surfaces of the source electrode layer and the drain electrode layer and provided over the gate electrode layer with the gate insulating layer therebetween, a conductive layer provided over part of the oxide semiconductor layer and having a lower resistance than the source electrode layer and the drain electrode layer, and an oxide insulating layer in contact with part of the oxide semiconductor layer.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 11, 2024
    Inventors: Masayuki SAKAKURA, Yoshiaki OIKAWA, Shunpei YAMAZAKI, Junichiro SAKATA, Masashi TSUBUKU, Kengo AKIMOTO, Miyuki HOSOBA