Patents by Inventor Masashi Yanagita
Masashi Yanagita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230207678Abstract: A semiconductor device includes a barrier layer, a channel layer, a regrowth layer, a vacancy generation region, and a source electrode or a drain electrode. The barrier layer includes a first nitride semiconductor. The channel layer includes a second nitride semiconductor and is bonded to the barrier layer at a first surface. The regrowth layer includes an n-type nitride semiconductor and is provided in a region dug deeper than an interface between the barrier layer and the channel layer from a second surface of the barrier layer. The second surface is on opposite side to the first surface. The vacancy generation region includes a nitrogen-capturing element and is provided in a region of the regrowth layer shallower than the interface between the barrier layer and the channel layer. The source electrode or the drain electrode is provided on the regrowth layer.Type: ApplicationFiled: April 16, 2021Publication date: June 29, 2023Inventors: SEI FUKUSHIMA, YUYA KANITANI, MASASHI YANAGITA
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Patent number: 11682720Abstract: [Overview] [Problem to be Solved] To provide a switching transistor and a semiconductor module having lower distortion generated in a signal. [Solution] A switching transistor including: a channel layer including a compound semiconductor and having sheet electron density equal to or higher than 1.7×1013 cm?2; a barrier layer formed on the channel layer by using a compound semiconductor that is of a different type from the channel layer; a gate electrode provided on the barrier layer; and a source electrode and a drain electrode provided on the barrier layer with the gate electrode interposed between the source electrode and the drain electrode.Type: GrantFiled: March 20, 2019Date of Patent: June 20, 2023Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Satoshi Taniguchi, Masashi Yanagita, Katsuhiko Takeuchi, Shigeru Kanematsu, Takanori Higashi
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Publication number: 20220416065Abstract: A semiconductor device includes a channel layer, a barrier layer, and at least one contact layer. The channel layer includes a GaN-based material. The barrier layer includes an AlInN-based material in which a composition ratio of In is higher than 18%, and is provided on the channel layer. The at least one contact layer includes a conductive-type semiconductor material and is provided to penetrate the barrier layer and reach the channel layer.Type: ApplicationFiled: November 13, 2020Publication date: December 29, 2022Inventor: MASASHI YANAGITA
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Publication number: 20220278210Abstract: A semiconductor device includes: a semiconductor layer including a channel layer; a contact region provided at a predetermined size in a thickness direction of the semiconductor layer, and having an impurity concentration that is higher than an impurity concentration of the surrounding semiconductor layer; a gate electrode facing the channel layer, and provided on the semiconductor layer and spaced from the contact region; and an electrode that is in contact with the semiconductor layer and electrically coupled to the channel layer via the contact region, and extending more on at least the gate electrode side than the contact region.Type: ApplicationFiled: July 17, 2020Publication date: September 1, 2022Inventors: Katsuhiko Takeuchi, Masashi Yanagita
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Publication number: 20210359120Abstract: A semiconductor device includes: a semiconductor substrate; a channel layer on the semiconductor substrate; a barrier layer on the channel layer; a gate electrode on the barrier layer via a gate insulating film; a source electrode and a drain electrode on the channel layer with the gate electrode interposed therebetween; a substrate opening that penetrates the channel layer and exposes the semiconductor substrate; an insulating film provided from upper parts of the gate electrode, the source electrode, and the drain electrode to an inner side of the substrate opening; and a wiring line layer on the insulating film, and electrically coupled to one of the gate electrode, the source electrode, and the drain electrode via an opening on the insulating film, in which at least a portion of the substrate opening is in an activation region in which the gate electrode, the source electrode, and the drain electrode are provided.Type: ApplicationFiled: September 20, 2019Publication date: November 18, 2021Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Katsuji MATSUMOTO, Masashi YANAGITA
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Patent number: 11127743Abstract: A transistor including a carrier transit layer that includes a compound semiconductor and a carrier supply layer in contact with the carrier transit layer. The carrier supply layer includes a compound semiconductor of a different type from the carrier transit layer. The transistor includes a gate electrode provided on the carrier supply layer, and a source electrode and a drain electrode provided on another surface of the carrier transit layer that is opposite to one surface on which the carrier supply layer is provided.Type: GrantFiled: November 4, 2016Date of Patent: September 21, 2021Assignee: SONY CORPORATIONInventors: Shigeru Kanematsu, Katsuhiko Takeuchi, Masashi Yanagita, Shinichi Wada
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Publication number: 20210111277Abstract: [Overview] [Problem to be Solved] To provide a switching transistor and a semiconductor module having lower distortion generated in a signal. [Solution] A switching transistor including: a channel layer including a compound semiconductor and having sheet electron density equal to or higher than 1.7×1013 cm?2; a barrier layer formed on the channel layer by using a compound semiconductor that is of a different type from the channel layer; a gate electrode provided on the barrier layer; and a source electrode and a drain electrode provided on the barrier layer with the gate electrode interposed between the source electrode and the drain electrode.Type: ApplicationFiled: March 20, 2019Publication date: April 15, 2021Inventors: SATOSHI TANIGUCHI, MASASHI YANAGITA, KATSUHIKO TAKEUCHI, SHIGERU KANEMATSU, TAKANORI HIGASHI
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Publication number: 20190035922Abstract: A semiconductor device includes a substrate and a first contact layer on the substrate. The semiconductor device includes a channel layer on the first contact layer and a barrier layer on the channel layer. The semiconductor device includes a gate electrode on at least one side surface of the barrier layer and a second contact layer on the channel layer. The semiconductor device includes a first electrode on the first contact layer and a second electrode on the second contact layer.Type: ApplicationFiled: January 13, 2017Publication date: January 31, 2019Applicant: SONY CORPORATIONInventors: Katsuhiko TAKEUCHI, Shigeru KANEMATSU, Masashi YANAGITA
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Publication number: 20180358359Abstract: [Object] To provide a transistor, a semiconductor device, and an electronic apparatus with reduced parasitic resistance. [Solution] A transistor including: a carrier transit layer including a compound semiconductor; a carrier supply layer provided on and in contact with the carrier transit layer and including a compound semiconductor of a different type from the carrier transit layer; a gate electrode provided on the carrier supply layer; and a source electrode and a drain electrode provided on another surface of the carrier transit layer that is opposite to one surface on which the carrier supply layer is provided.Type: ApplicationFiled: November 4, 2016Publication date: December 13, 2018Inventors: SHIGERU KANEMATSU, KATSUHIKO TAKEUCHI, MASASHI YANAGITA, SHINICHI WADA
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Patent number: 9257574Abstract: A diode includes a first semiconductor layer configured by a compound semiconductor containing impurities of a first conductivity type; a high dislocation density region; a second semiconductor layer which is laminated on the first semiconductor layer, which is lower in a concentration of impurities in a region of a side of an interface with the first semiconductor layer than that of the first semiconductor layer, and which has an opening in which a portion which corresponds to the high dislocation density region is removed; an insulating film pattern which is provided to cover an inner wall of the opening; an electrode which is provided so as to cover the insulating film pattern and to contact the second semiconductor layer; and an opposing electrode which is provided to interpose the first semiconductor layer, the second semiconductor layer and the insulating film pattern between the electrode and the opposing electrode.Type: GrantFiled: August 21, 2013Date of Patent: February 9, 2016Assignee: SONY CORPORATIONInventors: Shigeru Kanematsu, Masashi Yanagita
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Patent number: 9087888Abstract: A semiconductor device includes: a device region having a semiconductor layer that includes a channel section; a device peripheral region adjoining the device region; a gate electrode provided within the device region, and having a boundary section that spans the device region and the device peripheral region; a conductive layer provided between the gate electrode and the semiconductor layer; and an insulating layer provided between the gate electrode in the boundary section and the semiconductor layer.Type: GrantFiled: February 25, 2014Date of Patent: July 21, 2015Assignee: Sony CorporationInventors: Masashi Yanagita, Shigeru Kanematsu
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Patent number: 8907375Abstract: A method of manufacturing a semiconductor device includes the steps of forming a gate electrode of a transistor on an insulator layer on a surface of a semiconductor substrate, forming an isolation region by performing ion implantation of an impurity of a first conductivity type into the semiconductor substrate, forming a lightly doped drain region by performing, after forming a mask pattern including an opening portion narrower than a width of the gate electrode on an upper layer of the gate electrode of the transistor, ion implantation of an impurity of a second conductivity type near the surface of the semiconductor substrate with the mask pattern as a mask, and forming a source region and a drain region of the transistor by performing ion implantation of an impurity of the second conductivity type into the semiconductor substrate after forming the gate electrode of the transistor.Type: GrantFiled: March 29, 2013Date of Patent: December 9, 2014Assignee: Sony CorporationInventor: Masashi Yanagita
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Publication number: 20140252417Abstract: A semiconductor device includes: a device region having a semiconductor layer that includes a channel section; a device peripheral region adjoining the device region; a gate electrode provided within the device region, and having a boundary section that spans the device region and the device peripheral region; a conductive layer provided between the gate electrode and the semiconductor layer; and an insulating layer provided between the gate electrode in the boundary section and the semiconductor layer.Type: ApplicationFiled: February 25, 2014Publication date: September 11, 2014Applicant: Sony CorporationInventors: Masashi Yanagita, Shigeru Kanematsu
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Publication number: 20140061846Abstract: A diode includes a first semiconductor layer configured by a compound semiconductor containing impurities of a first conductivity type; a high dislocation density region; a second semiconductor layer which is laminated on the first semiconductor layer, which is lower in a concentration of impurities in a region of a side of an interface with the first semiconductor layer than that of the first semiconductor layer, and which has an opening in which a portion which corresponds to the high dislocation density region is removed; an insulating film pattern which is provided to cover an inner wall of the opening; an electrode which is provided so as to cover the insulating film pattern and to contact the second semiconductor layer; and an opposing electrode which is provided to interpose the first semiconductor layer, the second semiconductor layer and the insulating film pattern between the electrode and the opposing electrode.Type: ApplicationFiled: August 21, 2013Publication date: March 6, 2014Applicant: Sony CorporationInventors: Shigeru Kanematsu, Masashi Yanagita
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Patent number: 8426287Abstract: A method of manufacturing a semiconductor device includes the steps of forming a gate electrode of a transistor on an insulator layer on a surface of a semiconductor substrate, forming an isolation region by performing ion implantation of an impurity of a first conductivity type into the semiconductor substrate, forming a lightly doped drain region by performing, after forming a mask pattern including an opening portion narrower than a width of the gate electrode on an upper layer of the gate electrode of the transistor, ion implantation of an impurity of a second conductivity type near the surface of the semiconductor substrate with the mask pattern as a mask, and forming a source region and a drain region of the transistor by performing ion implantation of an impurity of the second conductivity type into the semiconductor substrate after forming the gate electrode of the transistor.Type: GrantFiled: November 12, 2010Date of Patent: April 23, 2013Assignee: Sony CorporationInventor: Masashi Yanagita
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Publication number: 20110127592Abstract: A method of manufacturing a semiconductor device includes the steps of forming a gate electrode of a transistor on an insulator layer on a surface of a semiconductor substrate, forming an isolation region by performing ion implantation of an impurity of a first conductivity type into the semiconductor substrate, forming a lightly doped drain region by performing, after forming a mask pattern including an opening portion narrower than a width of the gate electrode on an upper layer of the gate electrode of the transistor, ion implantation of an impurity of a second conductivity type near the surface of the semiconductor substrate with the mask pattern as a mask, and forming a source region and a drain region of the transistor by performing ion implantation of an impurity of the second conductivity type into the semiconductor substrate after forming the gate electrode of the transistor.Type: ApplicationFiled: November 12, 2010Publication date: June 2, 2011Applicant: SONY CORPORATIONInventor: Masashi Yanagita