Patents by Inventor Masashige Harada
Masashige Harada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10446111Abstract: An image data transfer system includes a receiver and a transmitter configured to sequentially receive compressed image data and sequentially transmit transmission data corresponding to the compressed image data to the receiver. The transmitter is configured to, in transmitting a specific transmission data, perform data comparison of bits of a compressed image body data of a specific compressed image data with bits of a previous transmission data transmitted over signal lines allocated to the compressed image body data, incorporate the compressed image body data of the specific compressed image data or the bit-inverted data corresponding thereto into the specific transmission data, in response to the result of the data comparison, and incorporate the compression code of the specific compressed image data into the specific transmission data independently of the result of the data comparison.Type: GrantFiled: January 23, 2017Date of Patent: October 15, 2019Assignee: Synaptics Japan GKInventors: Hirobumi Furihata, Masashige Harada, Iori Shiraishi, Takashi Nose
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Publication number: 20170221448Abstract: An image data transfer system includes a receiver and a transmitter configured to sequentially receive compressed image data and sequentially transmit transmission data corresponding to the compressed image data to the receiver. The transmitter is configured to, in transmitting a specific transmission data, perform data comparison of bits of a compressed image body data of a specific compressed image data with bits of a previous transmission data transmitted over signal lines allocated to the compressed image body data, incorporate the compressed image body data of the specific compressed image data or the bit-inverted data corresponding thereto into the specific transmission data, in response to the result of the data comparison, and incorporate the compression code of the specific compressed image data into the specific transmission data independently of the result of the data comparison.Type: ApplicationFiled: January 23, 2017Publication date: August 3, 2017Inventors: Hirobumi FURIHATA, Masashige HARADA, Iori SHIRAISHI, Takashi NOSE
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Patent number: 9269314Abstract: The display driver includes an image memory which is configured by including a plurality of memory mats, a plurality of power supply switches which can perform an ON and OFF control of power supply to each of the plurality of memory mats, and a control circuit which turns on or off the power supply switches. The control circuit turns on the plurality of power supply switches in such a manner that the power supply to the memory mat to which the image data is written at an initial time, among the plurality of memory mats, becomes stable earlier than the power supply to the other memory mats.Type: GrantFiled: April 5, 2014Date of Patent: February 23, 2016Assignee: Synaptics Display Devices GKInventors: Masashige Harada, Kunihiko Tani, Sosuke Suji
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Publication number: 20140313183Abstract: The display driver includes an image memory which is configured by including a plurality of memory mats, a plurality of power supply switches which can perform an ON and OFF control of power supply to each of the plurality of memory mats, and a control circuit which turns on or off the power supply switches. The control circuit turns on the plurality of power supply switches in such a manner that the power supply to the memory mat to which the image data is written at an initial time, among the plurality of memory mats, becomes stable earlier than the power supply to the other memory mats.Type: ApplicationFiled: April 5, 2014Publication date: October 23, 2014Applicant: Renesas SP Drivers Inc.Inventors: Masashige Harada, Kunihiko Tani, Sosuke Suji
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Patent number: 7710764Abstract: A semiconductor integrated circuit with memory redundancy circuit to address the problems of increased area, power consumption and access time which is caused by using an ECC circuit for error correction. The circuit includes: a plurality of memory mats; a local bus, parallel to word lines, which transfers read data and write data from memory cells; a global bus for writing, parallel to data lines, which transfers write data from an input pad IO; a global bus for reading, parallel to data lines, which transfers read data to an output pad IO; and at least one error correction circuit located at an intersection of the global buses and the local bus. Reading and writing may each be completed in a single cycle, and during a write operation, data which is different from data previously read is written. By this configuration, an increase in area and power consumption can be avoided and errors such as soft errors can be corrected.Type: GrantFiled: April 6, 2007Date of Patent: May 4, 2010Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Kenichi Osada, Koichiro Ishibashi, Yoshikazu Saitou, Masashige Harada, Takehiko Kijima
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Publication number: 20070286001Abstract: A semiconductor integrated circuit with memory redundancy circuit to address the problems of increased area, power consumption and access time which is caused by using an ECC circuit for error correction. The circuit comprises: a plurality of memory mats; a local bus, parallel to word lines, which transfers read data and write data from memory cells; a global bus for writing, parallel to data lines, which transfers write data from an input pad IO; a global bus for reading, parallel to data lines, which transfers read data to an output pad IO; and at least one error correction circuit located at an intersection of the global buses and the local bus. Reading and writing may each be completed in a single cycle, and during a write operation, data which is different from data previously read is written. By this configuration, an increase in area and power consumption can be avoided and errors such as soft errors can be corrected.Type: ApplicationFiled: April 6, 2007Publication date: December 13, 2007Inventors: Kenichi Osada, Koichiro Ishibashi, Yoshikazu Saitou, Masashige Harada, Takehiko Kijima
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Patent number: 7219272Abstract: A semiconductor integrated circuit with memory redundancy circuit to address the problems of increased area, power consumption and access time which is caused by using an ECC circuit for error correction. The circuit comprises: a plurality of memory mats; a local bus, parallel to word lines, which transfers read data and write data from memory cells; a global bus for writing, parallel to data lines, which transfers write data from an input pad IO; a global bus for reading, parallel to data lines, which transfers read data to an output pad IO; and at least one error correction circuit located at an intersection of the global buses and the local bus. Reading and writing may each be completed in a single cycle, and during a write operation, data which is different from data previously read is written. By this configuration, an increase in area and power consumption can be avoided and errors such as soft errors can be corrected.Type: GrantFiled: June 14, 2002Date of Patent: May 15, 2007Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co. Ltd.Inventors: Kenichi Osada, Koichiro Ishibashi, Yoshikazu Saitou, Masashige Harada, Takehiko Kijima
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Publication number: 20030008446Abstract: A semiconductor integrated circuit with memory redundancy circuit to address the problems of increased area, power consumption and access time which is caused by using an ECC circuit for error correction. The circuit comprises: a plurality of memory mats; a local bus, parallel to word lines, which transfers read data and write data from memory cells; a global bus for writing, parallel to data lines, which transfers write data from an input pad IO; a global bus for reading, parallel to data lines, which transfers read data to an output pad IO; and at least one error correction circuit located at an intersection of the global buses and the local bus. Reading and writing may each be completed in a single cycle, and during a write operation, data which is different from data previously read is written. By this configuration, an increase in area and power consumption can be avoided and errors such as soft errors can be corrected.Type: ApplicationFiled: June 14, 2002Publication date: January 9, 2003Applicant: Hitachi, Ltd.Inventors: Kenichi Osada, Koichiro Ishibashi, Yoshikazu Saitou, Masashige Harada, Takehiko Kijima
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Patent number: 6271687Abstract: A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the latch circuit, and a current source connected in series to the latch circuit and NMOS transistor pair. The NMOS transistors amplify a small voltage difference of input signals, and the inverters of the latch circuit further amplify the resulting voltage difference to produce the output signals. Based on a small voltage difference of input signals being amplified in two stages and the amplifying circuit being 2-stage serial connection of the current source and the NMOS transistor or CMOS inverter, the delay time of output response can be reduced.Type: GrantFiled: March 21, 2000Date of Patent: August 7, 2001Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Hiroshi Toyoshima, Masashige Harada, Tomohiro Nagano, Yoji Nishio, Atsushi Hiraishi, Kunihiro Komiyaji, Hideharu Yahata, Kenichi Fukui, Hirofumi Zushi, Takahiro Sonoda, Haruko Kawachino, Sadayuki Morita
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Patent number: 6046609Abstract: A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the latch circuit, and a current source connected in series to the latch circuit and NMOS transistor pair. The NMOS transistors amplify a small voltage difference of input signals, and the inverters of the latch circuit further amplify the resulting voltage difference to produce the output signals. Based on is a small voltage difference of input signals being amplified in two stages and the amplifying circuit being a 2-stage serial connection of the current source and the NMOS transistor or CMOS inverter, the delay time of output response can be reduced.Type: GrantFiled: November 10, 1998Date of Patent: April 4, 2000Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Hiroshi Toyoshima, Masashige Harada, Tomohiro Nagano, Yoji Nishio, Atsushi Hiraishi, Kunihiro Komiyaji, Hideharu Yahata, Kenichi Fukui, Hirofumi Zushi, Takahiro Sonoda, Haruko Kawachino, Sadayuki Morita
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Patent number: 5936909Abstract: A static RAM has plurality of memory mats each including a plurality of static memory cells formed in a matrix pattern at points of intersection between a plurality of word lines and a plurality of data lines. upon receipt of an address signal into an address register, an address selection circuit selects a memory cell in one of the memory mats, and connects the selected memory cell to a sense amplifier or a write amplifier furnished corresponding to the memory mat in question. At the same time, an address counter generates an address signal corresponding to the address signal by which one of the memory mats has been selected. When a burst mode is designated by a control signal, the address signal admitted to the address register is used to select a memory cell in a first memory mat. The selected memory cell is connected to the corresponding sense amplifier or write amplifier.Type: GrantFiled: January 27, 1998Date of Patent: August 10, 1999Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Takahiro Sonoda, Sadayuki Morita, Hirofumi Zushi, Haruko Kawachino, Hideharu Yahata, Kenichi Fukui, Tomohiro Nagano, Masashige Harada
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Patent number: 5854562Abstract: A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the latch circuit, and a current source connected in series to the latch circuit and NMOS transistor pair. The NMOS transistors amplify a small voltage difference of input signals, and the inverters of the latch circuit further amplify the resulting voltage difference to produce the output signals. Based on is a small voltage difference of input signals being amplified in two stages and the amplifying circuit being of 2-stage serial connection of the current source and the NMOS transistor or CMOS inverter, the delay time of output response can be reduced.Type: GrantFiled: April 15, 1997Date of Patent: December 29, 1998Assignees: Hitachi, Ltd, Hitachi ULSI Engineering Corp.Inventors: Hiroshi Toyoshima, Masashige Harada, Tomohiro Nagano, Yoji Nishio, Atsushi Hiraishi, Kunihiro Komiyaji, Hideharu Yahata, Kenichi Fukui, Hirofumi Zushi, Takahiro Sonoda, Haruko Kawachino, Sadayuki Morita