Patents by Inventor Masataka Higashiwaki

Masataka Higashiwaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11563092
    Abstract: A Ga2O3-based semiconductor device includes a Ga2O3-based crystal layer including a donor, and an N-doped region formed in at least a part of the Ga2O3-based crystal layer.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: January 24, 2023
    Assignees: National Institute of Information and Communications Technology, Tamura Corporation, Novel Crystal Technology, Inc
    Inventors: Masataka Higashiwaki, Yoshiaki Nakata, Takafumi Kamimura, Man Hoi Wong, Kohei Sasaki, Daiki Wakimoto
  • Patent number: 11264241
    Abstract: A semiconductor substrate includes a single crystal Ga2O3-based substrate and a polycrystalline substrate that are bonded to each other. A thickness of the single crystal Ga2O3-based substrate is smaller than a thickness of the polycrystalline substrate, and a fracture toughness value of the polycrystalline substrate is higher than a fracture toughness value of the single crystal Ga2O3-based substrate.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: March 1, 2022
    Assignees: TAMURA CORPORATION, SICOXS Corporation, National Institute of Information and Commnications Technology
    Inventors: Akito Kuramata, Shinya Watanabe, Kohei Sasaki, Kuniaki Yagi, Naoki Hatta, Masataka Higashiwaki, Keita Konishi
  • Patent number: 11081598
    Abstract: A trench MOS Schottky diode includes a first semiconductor layer including a Ga2O3-based single crystal, a second semiconductor layer that is a layer laminated on the first semiconductor layer and that includes a Ga2O3-based single crystal and a trench opened on a surface thereof opposite to the first semiconductor layer, an anode electrode formed on the surface of the second semiconductor layer, a cathode electrode formed on a surface of the first semiconductor layer, an insulating film covering an inner surface of the trench, and a trench MOS gate that is buried in the trench so as to be covered with the insulating film and is in contact with the anode electrode. The second semiconductor layer includes a lower layer on a side of the first semiconductor layer and an upper layer on a side of the anode electrode having a higher donor concentration than the lower layer.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: August 3, 2021
    Assignees: TAMURA CORPORATION, NOVEL CRYSTAL TECHNOLOGY, INC.
    Inventors: Kohei Sasaki, Masataka Higashiwaki
  • Patent number: 10861945
    Abstract: A semiconductor element includes a high-resistivity substrate that includes a ?-Ga2O3-based single crystal including an acceptor impurity, a buffer layer on the high-resistivity substrate, the buffer layer including a ?-Ga2O3-based single crystal, and a channel layer on the buffer layer, the channel layer including a ?-Ga2O3-based single crystal including a donor impurity. A crystalline laminate structure includes a high-resistivity substrate that includes a ?-Ga2O3-based single crystal including an acceptor impurity, a buffer layer on the high-resistivity substrate, the buffer layer including a ?-Ga2O3-based single crystal, and a donor impurity-containing layer on the buffer layer, the donor impurity-containing layer including a ?-Ga2O3-based single crystal including a donor impurity.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: December 8, 2020
    Assignees: TAMURA CORPORATION, NATIONAL INSTITUTE OF INFORMATION AND COMMUNICATIONS TECHNOLOGY, NATIONAL UNIVERSITY CORPORATION TOKYO UNIVERSITY OF AGRICULTURE AND TECHNOLOGY
    Inventors: Kohei Sasaki, Ken Goto, Masataka Higashiwaki, Man Hoi Wong, Akinori Koukitu, Yoshinao Kumagai, Hisashi Murakami
  • Patent number: 10825935
    Abstract: A trench MOS-type Schottky diode includes a first semiconductor layer including a Ga2O3-based single crystal, a second semiconductor layer that is a layer laminated on the first semiconductor layer and that includes a Ga2O3-based single crystal and a trench opened on a surface thereof opposite to the first semiconductor layer, an anode electrode formed on the surface of the second semiconductor layer opposite to the first semiconductor layer, a cathode electrode formed on a surface of the first semiconductor layer opposite to the second semiconductor layer, an insulating film covering the inner surface of the trench of the second semiconductor layer, and a trench MOS gate that is embedded in the trench of the second semiconductor layer so as to be covered with the insulating film and is in contact with the anode electrode.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: November 3, 2020
    Assignees: TAMURA CORPORATION, National Institute of Information and Communications Technology
    Inventors: Kohei Sasaki, Masataka Higashiwaki
  • Publication number: 20200168460
    Abstract: A semiconductor substrate includes a single crystal Ga2O3-based substrate and a polycrystalline substrate that are bonded to each other. A thickness of the single crystal Ga2O3-based substrate is smaller than a thickness of the polycrystalline substrate, and a fracture toughness value of the polycrystalline substrate is higher than a fracture toughness value of the single crystal Ga2O3-based substrate.
    Type: Application
    Filed: July 9, 2018
    Publication date: May 28, 2020
    Applicants: TAMURA CORPORATION, SICOXS Corporation, National Institute of Information and Communications Technology
    Inventors: Akito KURAMATA, Shinya WATANABE, Kohei SASAKI, Kuniaki YAGI, Naoki HATTA, Masataka HIGASHIWAKI, Keita KONISHI
  • Publication number: 20200144377
    Abstract: A Ga2O3-based semiconductor device includes a Ga2O3-based crystal layer including a donor, and an N-doped region formed in at least a part of the Ga2O3-based crystal layer.
    Type: Application
    Filed: April 26, 2018
    Publication date: May 7, 2020
    Applicants: NATIONAL INSTITUTE OF INFORMATION AND COMMUNICATIONS TECHNOLOGY, TAMURA CORPORATION, NOVEL CRYSTAL TECHNOLOGY, INC.
    Inventors: Masataka HIGASHIWAKI, Yoshiaki NAKATA, Takafumi KAMIMURA, Man Hoi WONG, Kohei SASAKI, Daiki WAKIMOTO
  • Publication number: 20200066921
    Abstract: A trench MOS Schottky diode includes a first semiconductor layer including a Ga2O3-based single crystal, a second semiconductor layer that is a layer laminated on the first semiconductor layer and that includes a Ga2O3-based single crystal and a trench opened on a surface thereof opposite to the first semiconductor layer, an anode electrode formed on the surface of the second semiconductor layer, a cathode electrode formed on a surface of the first semiconductor layer, an insulating film covering an inner surface of the trench, and a trench MOS gate that is buried in the trench so as to be covered with the insulating film and is in contact with the anode electrode. The second semiconductor layer includes a lower layer on a side of the first semiconductor layer and an upper layer on a side of the anode electrode having a higher donor concentration than the lower layer.
    Type: Application
    Filed: February 27, 2018
    Publication date: February 27, 2020
    Applicants: TAMURA CORPORATION, NOVEL CRYSTAL TECHNOLOGY, INC.
    Inventors: Kohei SASAKI, Masataka HIGASHIWAKI
  • Publication number: 20190148563
    Abstract: A trench MOS-type Schottky diode includes a first semiconductor layer including a Ga2O3-based single crystal, a second semiconductor layer that is a layer laminated on the first semiconductor layer and that includes a Ga2O3-based single crystal and a trench opened on a surface thereof opposite to the first semiconductor layer, an anode electrode formed on the surface of the second semiconductor layer opposite to the first semiconductor layer, a cathode electrode formed on a surface of the first semiconductor layer opposite to the second semiconductor layer, an insulating film covering the inner surface of the trench of the second semiconductor layer, and a trench MOS gate that is embedded in the trench of the second semiconductor layer so as to be covered with the insulating film and is in contact with the anode electrode.
    Type: Application
    Filed: April 20, 2017
    Publication date: May 16, 2019
    Applicants: TAMURA CORPORATION, National Institute of Information and Communications Technology
    Inventors: Kohei SASAKI, Masataka HIGASHIWAKI
  • Patent number: 10249767
    Abstract: A Ga2O3-based semiconductor element includes an undoped ?-Ga2O3 single crystal film disposed on a surface of a ?-Ga2O3 substrate, a source electrode and a drain electrode disposed on a same side of the undoped ?-Ga2O3 single crystal film, a gate electrode disposed on the undoped ?-Ga2O3 single crystal film between the source electrode and the drain electrode, and a region formed in the undoped ?-Ga2O3 single crystal film under the source electrode and the drain electrode and including a controlled dopant concentration.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: April 2, 2019
    Assignees: TAMURA CORPORATION, NATIONAL INSTITUTE OF INFORMATION AND COMMUNICATION TECHNOLOGY
    Inventors: Kohei Sasaki, Masataka Higashiwaki
  • Patent number: 10230007
    Abstract: A semiconductor element includes a base substrate that includes a Ga2O3-based crystal having a thickness of not less than 0.05 ?m and not more than 50 ?m, and an epitaxial layer that includes a Ga2O3-based crystal and is epitaxially grown on the base substrate. A semiconductor element includes an epitaxial layer that includes a Ga2O3-based crystal including an n-type dopant, an ion implanted layer that is formed on a surface of the epitaxial layer and includes a higher concentration of n-type dopant than the epitaxial layer, an anode electrode connected to the epitaxial layer, and a cathode electrode connected to the ion implanted layer.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: March 12, 2019
    Assignees: TAMURA CORPORATION, NATIONAL INSTITUTE OF INFORMATION AND COMMUNICATIONS TECHNOLOGY
    Inventors: Kohei Sasaki, Akito Kuramata, Masataka Higashiwaki
  • Patent number: 10199512
    Abstract: A high withstand voltage Schottky barrier diode includes a first layer that includes a first Ga2O3-based single crystal including a first Group IV element and Cl at a concentration of not more than 5×1016 cm?3 and that has an effective donor concentration of not less than 1×1013 and not more than 6.0×1017 cm?3, a second layer that includes a second Ga2O3-based single crystal including a second Group IV element and that has a higher effective donor concentration than the first layer and is laminated on the first layer, an anode electrode formed on the first layer, and a cathode electrode formed on the second layer.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: February 5, 2019
    Assignees: TAMURA CORPORATION, NATIONAL INSTITUTE OF INFORMATION AND COMMUNICATIONS TECHNOLOGY, NATIONAL UNIVERSITY CORPORATION TOKYO UNIVERSITY OF AGRICULTURE AND TECHNOLOGY
    Inventors: Kohei Sasaki, Ken Goto, Masataka Higashiwaki, Akinori Koukitu, Yoshinao Kumagai, Hisashi Murakami
  • Publication number: 20180350967
    Abstract: A semiconductor element includes a Molecular Beam Epitaxy (MBE)-grown channel layer including a ?-Ga2O3 single crystal layer. The MBE-grown channel layer is formed on a ?-Ga2O3 single crystal substrate.
    Type: Application
    Filed: July 23, 2018
    Publication date: December 6, 2018
    Inventors: Kohei SASAKI, Masataka Higashiwaki
  • Publication number: 20180254355
    Abstract: A high withstand voltage Schottky barrier diode includes a first layer that includes a first Ga2O3-based single crystal including a first Group IV element and Cl at a concentration of not more than 5×1016 cm?3 and that has an effective donor concentration of not less than 1×1013 and not more than 6.0×1017 cm?3, a second layer that includes a second Ga2O3-based single crystal including a second Group IV element and that has a higher effective donor concentration than the first layer and is laminated on the first layer, an anode electrode formed on the first layer, and a cathode electrode formed on the second layer.
    Type: Application
    Filed: March 9, 2016
    Publication date: September 6, 2018
    Applicants: TAMURA CORPORATION, National Institute of Information and Communications Technology, National University Corporation Tokyo University of Agriculture and Technology
    Inventors: Kohei SASAKI, Ken GOTO, Masataka HIGASHIWAKI, Akinori KOUKITU, Yoshinao KUMAGAI, Hisashi MURAKAMI
  • Publication number: 20170288061
    Abstract: A semiconductor element includes a high-resistivity substrate that includes a ?-Ga2O3-based single crystal including an acceptor impurity, an undoped ?-Ga2O3-based single crystal layer formed on the high-resistivity substrate, and an n-type channel layer that includes a side surface surrounded by the undoped ?-Ga2O3-based single crystal layer. The undoped ?-Ga2O3-based single crystal layer includes an element isolation region.
    Type: Application
    Filed: August 6, 2015
    Publication date: October 5, 2017
    Inventors: Kohei SASAKI, Masataka HIGASHIWAKI, Man Hoi WONG
  • Publication number: 20170278933
    Abstract: A semiconductor element includes a high-resistivity substrate that includes a ?-Ga2O3-based single crystal including an acceptor impurity, a buffer layer on the high-resistivity substrate, the buffer layer including a ?-Ga2O3-based single crystal, and a channel layer on the buffer layer, the channel layer including a ?-Ga2O3-based single crystal including a donor impurity. A crystalline laminate structure includes a high-resistivity substrate that includes a ?-Ga2O3-based single crystal including an acceptor impurity, a buffer layer on the high-resistivity substrate, the buffer layer including a ?-Ga2O3-based single crystal, and a donor impurity-containing layer on the buffer layer, the donor impurity-containing layer including a ?-Ga2O3-based single crystal including a donor impurity.
    Type: Application
    Filed: August 18, 2015
    Publication date: September 28, 2017
    Inventors: Kohei SASAKI, Ken GOTO, Masataka HIGASHIWAKI, Man Hoi WONG, Akinori KOUKITO, Yoshinao KUMAGAI, Hisashi MURAKAMI
  • Publication number: 20170213918
    Abstract: A semiconductor element includes a base substrate that includes a Ga2O3-based crystal having a thickness of not less than 0.05 ?m and not more than 50 ?m, and an epitaxial layer that includes a Ga2O3-based crystal and is epitaxially grown on the base substrate. A semiconductor element includes an epitaxial layer that includes a Ga2O3-based crystal including an n-type dopant, an ion implanted layer that is formed on a surface of the epitaxial layer and includes a higher concentration of n-type dopant than the epitaxial layer, an anode electrode connected to the epitaxial layer, and a cathode electrode connected to the ion implanted layer.
    Type: Application
    Filed: July 24, 2015
    Publication date: July 27, 2017
    Applicants: TAMURA CORPORATION, National Institute of Information and Communications Technology
    Inventors: Kohei SASAKI, Akito KURAMATA, Masataka HIGASHIWAKI
  • Patent number: 9611567
    Abstract: Provided is a method for controlling a donor concentration in a Ga2O3-based single crystal body. In addition, an ohmic contact having a low resistance is formed between a Ga2O3-based single crystal body and an electrode. A donor concentration in a Ga2O3-based single crystal body is controlled by a method which includes a step wherein Si, which serves as a donor impurity, is introduced into the Ga2O3-based single crystal body by an ion implantation method at an implantation concentration of 1×1020 cm?3 or less, so that a donor impurity implanted region is formed in the Ga2O3-based single crystal body, the donor impurity implanted region having a higher donor impurity concentration than the regions into which Si is not implanted, and a step wherein Si in the donor impurity implanted region is activated by annealing, so that a high donor concentration region is formed.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: April 4, 2017
    Assignees: TAMURA CORPORATION, NATIONAL INSTITUTE OF INFORMATION AND COMMUNICATIONS TECHNOLOGY
    Inventors: Kohei Sasaki, Masataka Higashiwaki
  • Publication number: 20160365418
    Abstract: A Ga2O3-based semiconductor element includes a ?-Ga2O3 substrate including a first conductivity type, a first ?-Ga2O3 single crystal film formed on the ?-Ga2O3 substrate, a second ?-Ga2O3 single crystal film including a second conductivity type formed on the first ?-Ga2O3 single crystal film, a source electrode formed on the second ?-Ga2O3 single crystal film, a drain electrode formed on a surface of the ?-Ga2O3 substrate opposite to the first ?-Ga2O3 single crystal film, and a gate electrode formed via a gate insulating film in a trench formed in the second ?-Ga2O3 single crystal film.
    Type: Application
    Filed: August 29, 2016
    Publication date: December 15, 2016
    Inventors: Kohei Sasaki, Masataka Higashiwaki
  • Publication number: 20160300953
    Abstract: A Ga2O3-based semiconductor element includes an undoped ?-Ga2O3 single crystal film disposed on a surface of a ?-Ga2O3 substrate, a source electrode and a drain electrode disposed on a same side of the undoped ?-Ga2O3 single crystal film, a gate electrode disposed on the undoped ?-Ga2O3 single crystal film between the source electrode and the drain electrode, and a region formed in the undoped ?-Ga2O3 single crystal film under the source electrode and the drain electrode and including a controlled dopant concentration.
    Type: Application
    Filed: June 15, 2016
    Publication date: October 13, 2016
    Inventors: Kohei Sasaki, Masataka Higashiwaki