Abstract: Overhead is significant when a timestamp according to a reference time is inserted. In view of this, there is provided an LSI which includes: a first time information conversion unit which converts, into time information of a reference time, time information from a first trace data source; a second time information conversion unit which converts, into time information of a reference time, time information from a second trace data source; and a packet merging unit.

Abstract: States of LSI internal signals (100 to 107) are monitored. Signal name information (31), signal state information (32), and information (33) about time in an LSI when a signal undergoes a state transition, are packetized and output as trace information (10) to the outside. In a development supporting device, the trace information (10) is decoded, the time information of the LSI is converted into real-time information, and based on the resultant information, a waveform of an LSI internal signal is reproduced. A plurality of LSI internal signals can be traced using terminals (16) the number of which is smaller than the number of the signals to be traced.

Abstract: After power-on, the start-up of a CPU 112 is suppressed by a microcomputer start-up suppressing/DMA start-up controlling device 101. Before the start-up of the CPU 112, a program read by a memory card I/F 103 is written in a writable ROM 105 by a DMA controlling device 102. After the start-up of the CPU 112, the CPU 112 executes the program written in the writable ROM 105.

Abstract: A memory control unit and a memory unit is connected to each other by a bus used for transfer of address, data and control signals. The memory control unit outputs a first command including a first predetermined location in the memory unit, to the memory unit. The memory control unit outputs a second command including a second predetermined location in the memory unit, to the memory unit when a predetermined time period has elapsed since the output of the first command.

Abstract: A cross-bus switch apparatus which establishes simultaneously two or more pairs of connections between (i) a source bus arbitrarily selected from a plurality of source buses connected to one or more source apparatuses and (ii) a destination bus arbitrarily selected from a plurality of destination buses connected to one or more destination apparatuses. The cross-bus switch apparatus includes: a plurality of cross-bus switch units. The plurality of source buses are grouped into a plurality of source bus groups which are each connected to one of the plurality of cross-bus switch units. The plurality of destination buses are grouped into a plurality of destination bus groups which are each connected to one of the plurality of cross-bus switch units. Each cross-bus switch unit is connected to either (i) a source bus group or a destination bus group, or (ii) a source bus group and a destination bus group.

Abstract: A memory control unit and a memory unit is connected to each other by a bus used for transfer of address, data and control signals. The memory control unit outputs a first command including a first predetermined location in the memory unit, to the memory unit. The memory control unit outputs a second command including a second predetermined location in the memory unit, to the memory unit when a predetermined time period has elapsed since the output of the first command.

Abstract: A memory control device for arbitrating memory access contention among bus masters while ensuring, regarding each bus master, the required transfer rate within the required time margin. A device external to LSI 100 writes into the transfer rate information storage unit 111 the transfer rate information indicating the transfer rate and the time period within which the transfer rate is to be ensured. In response, the timing information generator unit 112 determines the shortest time period as a cycle, and also determines, regarding each bus master, time taken to ensure the required transfer rate based on the memory bus bandwidth as a bus use permission time period. The arbiter unit 114 grants the bus use right sequentially with the passage of time to each bus master issuing a bus request for the corresponding bus use permission time period.

Abstract: A system integrated circuit that identifies the cause of a malfunction even if the number of output terminals of a system LSI to be assigned to internal buses in the system LSI is strictly restricted. Comparators 11 to 15 are connected to any of a plurality of buses. Each comparator judges whether a certain expected value matches data transferred on a bus connected to the comparator. The selector unit 10 selects one of the plurality of buses in accordance with the judgement result of the comparator, and outputs data transferred on the selected bus to outside the system integrated circuit so that an observer can observe internal state of the system integrated circuit from outside.

Abstract: A parallel stream operation apparatus in which selecting keys for encrypting or decrypting stream data input in parallel is simplified. A plurality of paths that correspond respectively to a plurality of keys for encrypting and/or decrypting stream data are provided. Stream data received by a first interface is decrypted with a first decryption key, and stream data received by a second interface is decrypted with a second decryption key. An input stream processing unit outputs the stream data received by the first input unit to a first path corresponding to the first decryption key, and outputs the stream data received by the second input unit to a second path corresponding to the second decryption key. An operation unit decrypts the stream data from the first path with the first decryption key and the stream data from the second path with the second decryption key.

Abstract: A vehicle-mounted display system including: a first display panel; a second display panel; an image data fetching unit operable to fetch first image data and second image data; a first display control unit operable to display the first image data on the first display panel; an instruction unit operable to issue an instruction to display a composite image; and a second display control unit operable to receive the instruction, generate the composite image by combining the first image data with the second image data, and display the composite image on the second display panel.

Abstract: A memory control device for arbitrating memory access contention among bus masters while ensuring, regarding each bus master, the required transfer rate within the required time margin. A device external to LSI 100 writes into the transfer rate information storage unit 111 the transfer rate information indicating the transfer rate and the time period within which the transfer rate is to be ensured. In response, the timing information generator unit 112 determines the shortest time period as a cycle, and also determines, regarding each bus master, time taken to ensure the required transfer rate based on the memory bus bandwidth as a bus use permission time period. The arbiter unit 114 grants the bus use right sequentially with the passage of time to each bus master issuing a bus request for the corresponding bus use permission time period.

Abstract: A digital broadcast receiving apparatus, for receiving a plurality of pieces of compressed still image data repeatedly transmitted from a digital broadcast transmitting apparatus and for outputting a still image selected by a user as a TV signal, fetches still image data into a main memory prior to a selecting operation made by the user, expands still image data of a still image selected by the user using an AV decoder of an MPEG decoder, and outputs an image signal of the selected still image according to the expanded still image data.

Abstract: In a system bus connected to at least one CPU having a cache memory used for increasing memory access speed in an engineering workstation or the like, a main memory controller including a status memory for storing owned and unowned statuses in a main memory and a cache memory of data associated with an access operation to a system bus connected to at least one CPU having a cache memory performed by an access means of a CPU or the like, a memory control portion which is responsive to signals indicative of the stored statuses for reading the data in the main memory before the time for outputting a data invalidating signal from the cache memory elapses in the case of the owned status and for reading the data in the cache memory after the data invalidating signal is output in the case of the unowned status, and a status rewrite control portion for monitoring accesses to the system bus and for rewriting the status in the status memory according to the result of the monitoring.