Abstract: In one embodiment, a semiconductor device includes a well region of a second conductivity type, a control electrode, a first main electrode and a second main electrode. The well region has a source region and a drain region of a first conductivity type selectively formed in a surface of the well region. The control electrode is configured to control a current path between the source region connected to the first main electrode and the drain region connected to the second main electrode. With respect to a reference defined as a position of the well region at an identical depth to a portion of the source region or the drain region with maximum curvature, a peak of impurity concentration distribution of the second conductivity type is in a range of 0.15 micrometers on a side of the surface of the well region and on a side opposite to the surface.

Abstract: A method of manufacturing a semiconductor device comprising the steps of: forming a first silicon oxide film which covers a first region on the top surface of a silicon substrate, but which does not cover a second region and a third region thereon; oxidizing the silicon substrate to thicken the first silicon oxide film formed on the first region, and to form a second silicon oxide film on the second region and the third region; forming a first silicon film which covers the first region and the second region, but which does not cover the third region; etching and removing the second silicon oxide film formed on the third region by using the first silicon film as a mask; and forming a third silicon oxide film on the third region, the third silicon oxide film being thinner than the second silicon oxide film.

Abstract: In one embodiment, a semiconductor device includes a well region of a second conductivity type, a control electrode, a first main electrode and a second main electrode. The well region has a source region and a drain region of a first conductivity type selectively formed in a surface of the well region. The control electrode is configured to control a current path between the source region connected to the first main electrode and the drain region connected to the second main electrode. With respect to a reference defined as a position of the well region at an identical depth to a portion of the source region or the drain region with maximum curvature, a peak of impurity concentration distribution of the second conductivity type is in a range of 0.15 micrometers on a side of the surface of the well region and on a side opposite to the surface.

Abstract: A semiconductor device including a nonvolatile memory and the fabrication method of the same is described formed on a semiconductor substrate. According to the semiconductor device, a second gate electrode film is used for a gate electrode film of a logic circuit, and for a control gate electrode film of a nonvolatile memory. As the second gate electrode film is formed at a relatively later step in fabrication, subsequent thermal process may be avoided. The gate structure is suitable for miniaturization of the transistor in the logic circuit.

Abstract: A semiconductor device including a nonvolatile memory and the fabrication method of the same is described formed on a semiconductor substrate. According to the semiconductor device, a second gate electrode film is used for a gate electrode film of a logic circuit, and for a control gate electrode film of a nonvolatile memory. As the second gate electrode film is formed at a relatively later step in fabrication, subsequent thermal process may be avoided. The gate structure is suitable for miniaturization of the transistor in the logic circuit.

Abstract: A semiconductor device including a nonvolatile memory and the fabrication method of the same is described formed on a semiconductor substrate. According to the semiconductor device, a second gate electrode film is used for a gate electrode film of a logic circuit, and for a control gate electrode film of a nonvolatile memory. As the second gate electrode film is formed at a relatively later step in fabrication, subsequent thermal process may be avoided. The gate structure is suitable for miniaturization of the transistor in the logic circuit.

Abstract: A method of manufacturing a semiconductor device comprising the steps of: forming a first silicon oxide film which covers a first region on the top surface of a silicon substrate, but which does not cover a second region and a third region thereon; oxidizing the silicon substrate to thicken the first silicon oxide film formed on the first region, and to form a second silicon oxide film on the second region and the third region; forming a first silicon film which covers the first region and the second region, but which does not cover the third region; etching and removing the second silicon oxide film formed on the third region by using the first silicon film as a mask; and forming a third silicon oxide film on the third region, the third silicon oxide film being thinner than the second silicon oxide film.

Abstract: A semiconductor device including a nonvolatile memory and the fabrication method of the same is described formed on a semiconductor substrate. According to the semiconductor device, a second gate electrode film is used for a gate electrode film of a logic circuit, and for a control gate electrode film of a nonvolatile memory. As the second gate electrode film is formed at a relatively later step in fabrication, subsequent thermal process may be avoided. The gate structure is suitable for miniaturization of the transistor in the logic circuit.

Abstract: A semiconductor device including a nonvolatile memory and the fabrication method of the same is described formed on a semiconductor substrate. According to the semiconductor device, a second gate electrode film is used for a gate electrode film of a logic circuit, and for a control gate electrode film of a nonvolatile memory. As the second gate electrode film is formed at a relatively later step in fabrication, subsequent thermal process may be avoided. The gate structure is suitable for miniaturization of the transistor in the logic circuit.

Abstract: A semiconductor device including a nonvolatile memory and the fabrication method of the same is described formed on a semiconductor substrate. According to the semiconductor device, a second gate electrode film is used for a gate electrode film of a logic circuit, and for a control gate electrode film of a nonvolatile memory. As the second gate electrode film is formed at a relatively later step in fabrication, subsequent thermal process may be avoided. The gate structure is suitable for miniaturization of the transistor in the logic circuit.

Abstract: A semiconductor device including a nonvolatile memory formed on a semiconductor substrate. According to the semiconductor device, a second gate electrode film is used for a gate electrode film of a logic circuit, and for a control gate electrode film of a nonvolatile memory. As the second gate electrode film is formed at a relatively later step in fabrication, subsequent thermal process may be avoided. The gate structure is suitable for miniaturization of the transistor in the logic circuit.

Abstract: A first side-wall film is formed on the sides of a gate electrode of a high-voltage transistor, and a second side-wall film is provided on the first side-wall film. The first side-wall film has an etching rate lower that of a pre-metal dielectric, and the second side-wall film has an etching rate substantially equal to that of the of the pre-metal dielectric. The LDD of the high-voltage transistor is provided in that part of the semiconductor substrate which lies right below the first and second side-wall films. The source/drain diffusion layer of the high-voltage transistor is formed in that part of the substrate which is outside the second side-wall film. A first side-wall film having an etching rate lower than that of the pre-metal dielectric and/or a second side-wall film having an etching rate substantially equal to that of the pre-metal dielectric are provided on the sides of the gate electrode of the low voltage transistor.

Abstract: A semiconductor device including a nonvolatile memory and the fabrication method of the same is described. According to the semiconductor device, a second gate electrode film is used for a gate electrode film of a logic circuit, and for a control gate electrode film of a nonvolatile memory. As the second gate electrode film is formed at a relatively later step in fabrication, subsequent thermal process may be avoided. The gate structure is suitable for miniaturization of the transistor in the logic circuit.

Abstract: A first side-wall film is formed on the sides of a gate electrode of a high-voltage transistor, and a second side-wall film is provided on the first side-wall film. The first side-wall film has an etching rate lower that of a pre-metal dielectric, and the second side-wall film has an etching rate substantially equal to that of the of the pre-metal dielectric. The LDD of the high-voltage transistor is provided in that part of the semiconductor substrate which lies right below the first and second side-wall films. The source/drain diffusion layer of the high-voltage transistor is formed in that part of the substrate which is outside the second side-wall film. A first side-wall film having an etching rate lower than that of the pre-metal dielectric and/or a second side-wall film having an etching rate substantially equal to that of the pre-metal dielectric are provided on the sides of the gate electrode of the low voltage transistor.

Abstract: In a semiconductor device in which a non-volatile memory element and a p-channel IGFET are mounted on a single substrate, a nitride atom density of a tunnel insulating film of the non-volatile memory element is set to be higher than a nitride atom density of a gate insulating film of the p-channel IGFET. With respect to a manufacturing method, a region where the gate insulating film of the p-channel IGFET is covered by a thick buffer silicon oxide film when nitrifying the tunnel insulating film of the non-volatile memory element. The buffer silicon oxide film can be reliably removed when the gate insulating film is formed, because no nitride film is made between the substrate and the buffer silicon oxide film.

Abstract: In a semiconductor device in which a non-volatile memory element and a p-channel IGFET are mounted on a single substrate, a nitride atom density of a tunnel insulating film of the non-volatile memory element is set to be higher than a nitride atom density of a gate insulating film of the p-channel IGFET. With respect to a manufacturing method, a region where the gate insulating film of the p-channel IGFET is covered by a thick buffer silicon oxide film when nitrifying the tunnel insulating film of the non-volatile memory element. The buffer silicon oxide film can be reliably removed when the gate insulating film is formed, because no nitride film is made between the substrate and the buffer silicon oxide film.

Abstract: A first side-wall film is formed on the sides of a gate electrode of a high-voltage transistor, and a second side-wall film is provided on the first side-wall film. The first side-wall film has an etching rate lower that of a pre-metal dielectric, and the second side-wall film has an etching rate substantially equal to that of the of the pre-metal dielectric. The LDD of the high-voltage transistor is provided in that part of the semiconductor substrate which lies right below the first and second side-wall films. The source/drain diffusion layer of the high-voltage transistor is formed in that part of the substrate which is outside the second side-wall film. A first side-wall film having an etching rate lower than that of the pre-metal dielectric and/or a second side-wall film having an etching rate substantially equal to that of the pre-metal dielectric are provided on the sides of the gate electrode of the low voltage transistor.

Abstract: In a semiconductor device in which a non-volatile memory element and a p-channel IGFET are mounted on a single substrate, a nitride atom density of a tunnel insulating film of the non-volatile memory element is set to be higher than a nitride atom density of a gate insulating film of the p-channel IGFET. With respect to a manufacturing method, a region where the gate insulating film of the p-channel IGFET is covered by a thick buffer silicon oxide film when nitrifying the tunnel insulating film of the non-volatile memory element. The buffer silicon oxide film can be reliably removed when the gate insulating film is formed, because no nitride film is made between the substrate and the buffer silicon oxide film.

Abstract: A first side-wall film is formed on the sides of a gate electrode of a high-voltage transistor, and a second side-wall film is provided on the first side-wall film. The first side-wall film has an etching rate lower that of a pre-metal dielectric, and the second side-wall film has an etching rate substantially equal to that of the of the pre-metal dielectric. The LDD of the high-voltage transistor is provided in that part of the semiconductor substrate which lies right below the first and second side-wall films. The source/drain diffusion layer of the high-voltage transistor is formed in that part of the substrate which is outside the second side-wall film. A first side-wall film having an etching rate lower than that of the pre-metal dielectric and/or a second side-wall film having an etching rate substantially equal to that of the pre-metal dielectric are provided on the sides of the gate electrode of the low voltage transistor.

Abstract: A first side-wall film is formed on the sides of a gate electrode of a high-voltage transistor, and a second side-wall film is provided on the first sidewall film. The first side-wall film has an etching rate lower that of a pre-metal dielectric, and the second side-wall film has an etching rate substantially equal to that of the of the pre-metal dielectric. The LDD of the high-voltage transistor is provided in that part of the semiconductor substrate which lies right below the first and second side-wall films. The source/drain diffusion layer of the high-voltage transistor is formed in that part of the substrate which is outside the second side-wall film. A first side-wall film having an etching rate lower than that of the pre-metal dielectric and/or a second side-wall film having an etching rate substantially equal to that of the pre-metal dielectric are provided on the sides of the gate electrode of the low voltage transistor.