Patents by Inventor Masataka TSUCHIMOTO

Masataka TSUCHIMOTO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10677838
    Abstract: An abnormal state latch unit comprises: an detection circuit that masks an abnormality position signal; a timer circuit that starts motion when the abnormality position signal indicates the occurrence of an abnormality based on the abnormality position signal, and completes the motion and outputs a reset signal after passage of a predetermined period; and a latch circuit that latches the abnormality position signal output from the detection circuit when the reset signal is output. The detection circuit masks the abnormality position signal when the latch circuit makes latching motion to disable an output from the detection circuit. The timer circuit masks an input to the timer circuit when the latch circuit makes the latching motion to maintain a state indicating completion of the motion. Abnormality voltage signals generated by an signal generation circuit are wired-OR connected and supplied through a single signal line to a monitor circuit.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: June 9, 2020
    Assignee: FANUC CORPORATION
    Inventor: Masataka Tsuchimoto
  • Publication number: 20190154752
    Abstract: An abnormal state latch unit comprises: an detection circuit that masks an abnormality position signal; a timer circuit that starts motion when the abnormality position signal indicates the occurrence of an abnormality based on the abnormality position signal, and completes the motion and outputs a reset signal after passage of a predetermined period; and a latch circuit that latches the abnormality position signal output from the detection circuit when the reset signal is output. The detection circuit masks the abnormality position signal when the latch circuit makes latching motion to disable an output from the detection circuit. The timer circuit masks an input to the timer circuit when the latch circuit makes the latching motion to maintain a state indicating completion of the motion. Abnormality voltage signals generated by an signal generation circuit are wired-OR connected and supplied through a single signal line to a monitor circuit.
    Type: Application
    Filed: October 29, 2018
    Publication date: May 23, 2019
    Applicant: FANUC CORPORATION
    Inventor: Masataka TSUCHIMOTO
  • Patent number: 10261483
    Abstract: In a digitally controlled power source, a setting value of an output voltage therefrom is set in advance in the vicinity of an upper limit within a tolerable range of fluctuation. Even if a voltage drop is caused by starting currents that flow upon initial rise of DC-DC converters in a subsequent stage, such setting makes it possible to confine values of the output voltage within the tolerable range of fluctuation because the setting value of the output voltage is set in advance at a relatively high value. Accordingly, the starting currents in the DC-DC converters can be increased without restriction so that rise time for the power source can be shortened.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: April 16, 2019
    Assignee: FANUC CORPORATION
    Inventors: Masataka Tsuchimoto, Shouhei Kobayashi
  • Publication number: 20170019020
    Abstract: In a digitally controlled power source, a setting value of an output voltage therefrom is set in advance in the vicinity of an upper limit within a tolerable range of fluctuation. Even if a voltage drop is caused by starting currents that flow upon initial rise of DC-DC converters in a subsequent stage, such setting makes it possible to confine values of the output voltage within the tolerable range of fluctuation because the setting value of the output voltage is set in advance at a relatively high value. Accordingly, the starting currents in the DC-DC converters can be increased without restriction so that rise time for the power source can be shortened.
    Type: Application
    Filed: July 13, 2016
    Publication date: January 19, 2017
    Inventors: Masataka TSUCHIMOTO, Shouhei KOBAYASHI
  • Patent number: 9484817
    Abstract: In a DC/DC converter, each channel operates under digital control using nonlinear control. The time interval between the time of turning ON of the switching element 1 and the time of turning ON of each of other switching elements j (j=2, 3, . . . , N) is measured. If the measured interval is within a specified range, operation is continued without changing the ON time of the switching element j used last time. Meanwhile, if the measured interval is out of the range, the ON time of the switching element j is increased or decreased within a predetermined range to be shifted from a basic frequency. Thus, the interval between the time of turning ON of the switching element 1 and the time of turning ON of the switching element j is brought back to the specified range.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: November 1, 2016
    Assignee: FANUC CORPORATION
    Inventors: Yoshinori Sakai, Masataka Tsuchimoto
  • Publication number: 20150349642
    Abstract: In a DC/DC converter, each channel operates under digital control using nonlinear control. The time interval between the time of turning ON of the switching element 1 and the time of turning ON of each of other switching elements j (j=2, 3, . . . , N) is measured. If the measured interval is within a specified range, operation is continued without changing the ON time of the switching element j used last time. Meanwhile, if the measured interval is out of the range, the ON time of the switching element j is increased or decreased within a predetermined range to be shifted from a basic frequency. Thus, the interval between the time of turning ON of the switching element 1 and the time of turning ON of the switching element j is brought back to the specified range.
    Type: Application
    Filed: May 29, 2015
    Publication date: December 3, 2015
    Inventors: Yoshinori SAKAI, Masataka TSUCHIMOTO