Patents by Inventor Masato Kanazawa
Masato Kanazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240163247Abstract: An edge control device (10) includes: an acquisition unit (15a) configured to acquire information about switching of an edge router accommodating a user's terminal; an instruction unit (15d) configured to instruct a dynamic host configuration protocol (DHCP) server to induce re-acquisition of an internet protocol (IP) address by the user's terminal on the basis of the information about edge router switching acquired by the acquisition unit (15a); and a receiving unit (15e) configured to receive, from a DHCP server, a notification that induction of IP address reacquisition is completed.Type: ApplicationFiled: February 16, 2021Publication date: May 16, 2024Inventors: Masato NISHIGUCHI, Satoshi NAKATSUKASA, Takahiro SHIBATA, Toshiyuki KANAZAWA, Hiroki IWAHASHI
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Publication number: 20240097980Abstract: A common control unit (141A) acquires a configuration input request to a communication device accommodating a user using a network. An individual control unit (142A) identifies a variable group necessary for a command to execute the configuration input based on request content of the configuration input received by the common control unit (141A) and a type of communication device and transmits the identified variable group to the common control unit (141A). A command execution unit (143A) acquires the variable group identified by the individual control unit (141A) from the common control unit (141A), generates a command based on the acquired variable group, and executes the generated command.Type: ApplicationFiled: February 16, 2021Publication date: March 21, 2024Inventors: Hiroki IWAHASHI, Takahiro SHIBATA, Toshiyuki KANAZAWA, Masato NISHIGUCHI
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Patent number: 11311579Abstract: The present invention provides a method for producing a cell culture for promoting angiogenesis or axon outgrowth, particularly for the treatment of a cerebrovascular disease, an ischemic cardiac disease or traumatic brain injury and spinal cord injury, which comprises culturing a cell population containing microglia and/or monocytes under conditions of low oxygen concentration and/or low sugar concentration to produce the culture, a cell preparation obtained by the method, and a method for treating a cerebrovascular disease, an ischemic cardiac disease or traumatic cerebrospinal neuropathy by using the cell preparation.Type: GrantFiled: August 30, 2017Date of Patent: April 26, 2022Assignee: NIIGATA UNIVERSITYInventors: Takayoshi Shimohata, Masato Kanazawa
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Patent number: 10890879Abstract: Provided is an electronic clock including: a power generator; a secondary battery, which is to be charged with electric power generated by the power generator; a balance information transmitter configured to transmit, to a computer, balance information relating to a transition of a power generation amount or a charging balance of the secondary battery; a connection time period setting module configured to set a connection time period of a connection with the computer based on the balance information; and a communication controller configured to control a start and an end of communication to/from the computer based on the connection time period.Type: GrantFiled: March 15, 2017Date of Patent: January 12, 2021Assignee: CITIZEN WATCH CO., LTD.Inventors: Yusuke Hirota, Masayuki Araki, Akiyoshi Kondoh, Masato Kanazawa
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Publication number: 20190216856Abstract: The present invention provides a method for producing a cell culture for promoting angiogenesis or axon outgrowth, particularly for the treatment of a cerebrovascular disease, an ischemic cardiac disease or traumatic brain injury and spinal cord injury, which comprises culturing a cell population containing microglia and/or monocytes under conditions of low oxygen concentration and/or low sugar concentration to produce the culture, a cell preparation obtained by the method, and a method for treating a cerebrovascular disease, an ischemic cardiac disease or traumatic cerebrospinal neuropathy by using the cell preparation.Type: ApplicationFiled: August 30, 2017Publication date: July 18, 2019Applicant: NIIGATA UNIVERSITYInventors: Takayoshi SHIMOHATA, Masato KANAZAWA
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Publication number: 20190079463Abstract: Provided is an electronic clock including: a power generator; a secondary battery, which is to be charged with electric power generated by the power generator; a balance information transmitter configured to transmit, to a computer, balance information relating to a transition of a power generation amount or a charging balance of the secondary battery; a connection time period setting module configured to set a connection time period of a connection with the computer based on the balance information; and a communication controller configured to control a start and an end of communication to/from the computer based on the connection time period.Type: ApplicationFiled: March 15, 2017Publication date: March 14, 2019Applicant: CITIZEN WATCH CO., LTD.Inventors: Yusuke HIROTA, Masayuki ARAKI, Akiyoshi KONDOH, Masato KANAZAWA
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Patent number: 7826913Abstract: A sheet metal factory processing system includes a production manager which generates a processing schedule for multiple units each including at least one material sheet, to manage the processing schedule on a per-unit basis. The processing schedule is generated based on sheet processing data obtained by allocating parts to be blanked from the material sheets according to a manufacturing designation. The sheet metal factory processing system also includes a sheet metal factory processing installation which is connected to the production manager through a communication network. The sheet metal factory processing installation receives the generated processing schedule from the production manager and executes the received processing schedule.Type: GrantFiled: March 1, 2007Date of Patent: November 2, 2010Assignee: Amada Company, LimitedInventors: Masato Kanazawa, Kaoru Nakamura
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Patent number: 7600750Abstract: A paper sheet carrying apparatus is provided that can remove a sheet remained in a path due to paper jam, etc. using a simple mechanism if a sheet remains in any one of two sheet paths or straddles both paths. A sheet path of a first unit is linked to that of a second unit by a linking device and a control mechanism is included that sends to the device and discharges a sheet stopped carrying from the path of the first unit to that of the second unit. When a sheet exists in the path of the second unit, it is carried in opposite direction to the linking device. When a sheet straddles both paths of the first and second units, it is carried to the linking device concurrently in forward direction in the path of the first unit and in opposite in that of the second unit.Type: GrantFiled: December 19, 2007Date of Patent: October 13, 2009Assignee: Sharp Kabushiki KaishaInventor: Masato Kanazawa
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Publication number: 20080157463Abstract: A paper sheet carrying apparatus is provided that can remove a sheet remained in a path due to paper jam, etc. using a simple mechanism if a sheet remains in any one of two sheet paths or straddles both paths. A sheet path of a first unit is linked to that of a second unit by a linking device and a control mechanism is included that sends to the device and discharges a sheet stopped carrying from the path of the first unit to that of the second unit. When a sheet exists in the path of the second unit, it is carried in opposite direction to the linking device. When a sheet straddles both paths of the first and second units, it is carried to the linking device concurrently in forward direction in the path of the first unit and in opposite in that of the second unit.Type: ApplicationFiled: December 19, 2007Publication date: July 3, 2008Inventor: Masato KANAZAWA
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Patent number: 7239931Abstract: A sheet metal factory processing system includes a production management apparatus which generates a processing schedule based on a manufacturing designation. The processing schedule is managed in each unit of material sheets. The sheet metal factory processing system also includes a sheet metal factory processing installation which is mutually connected to the production management apparatus through a communication network to execute the processing schedule received from the production management apparatus.Type: GrantFiled: November 10, 2004Date of Patent: July 3, 2007Assignee: Amada Company, LimitedInventors: Masato Kanazawa, Kaoru Nakamura
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Publication number: 20070150083Abstract: A sheet metal factory processing system includes a production manager which generates a processing schedule for multiple units each including at least one material sheet, to manage the processing schedule on a per-unit basis. The processing schedule is generated based on sheet processing data obtained by allocating parts to be blanked from the material sheets according to a manufacturing designation. The sheet metal factory processing system also includes a sheet metal factory processing installation which is connected to the production manager through a communication network. The sheet metal factory processing installation receives the generated processing schedule from the production manager and executes the received processing schedule.Type: ApplicationFiled: March 1, 2007Publication date: June 28, 2007Applicant: AMADA COMPANY, LIMITEDInventors: Masato KANAZAWA, Kaoru NAKAMURA
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Publication number: 20050107903Abstract: A sheet metal factory processing system includes a production management apparatus which generates a processing schedule based on a manufacturing designation. The processing schedule is managed in each unit of material sheets. The sheet metal factory processing system also includes a sheet metal factory processing installation which is mutually connected to the production management apparatus through a communication network to execute the processing schedule received from the production management apparatus.Type: ApplicationFiled: November 10, 2004Publication date: May 19, 2005Applicant: Amada Company, LimitedInventors: Masato Kanazawa, Kaoru Nakamura
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Patent number: 6713826Abstract: A gate electrode is made up of a lower electrode of polysilicon and an upper electrode including a low-resistance film. A nitride sidewall is formed to cover at least the side faces of an insulator cap and the upper electrode. A pad oxide film is formed to cover at least part of the side faces of the lower electrode and part of the upper surface of a semiconductor substrate. Since a second nitride sidewall is formed to cover the first nitride sidewall and the pad oxide film, a self-aligned contact hole can be formed by etching. As a result, a semiconductor device with a highly reliable self-aligned contact can be obtained.Type: GrantFiled: February 3, 2003Date of Patent: March 30, 2004Assignee: Matsushita Electric Industrial Co., LTDInventors: Takashi Uehara, Masato Kanazawa
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Publication number: 20030141554Abstract: A gate electrode is made up of a lower electrode of polysilicon and an upper electrode including a low-resistance film. A nitride sidewall is formed to cover at least the side faces of an insulator cap and the upper electrode. A pad oxide film is formed to cover at least part of the side faces of the lower electrode and part of the upper surface of a semiconductor substrate. Since a second nitride sidewall is formed to cover the first nitride sidewall and the pad oxide film, a self-aligned contact hole can be formed by etching. As a result, a semiconductor device with a highly reliable self-aligned contact can be obtained.Type: ApplicationFiled: February 3, 2003Publication date: July 31, 2003Applicant: MATSUSHITA ELECTRONICS CORPORATIONInventors: Takashi Uehara, Masato Kanazawa
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Patent number: 6573132Abstract: A gate electrode is made up of a lower electrode of polysilicon and an upper electrode including a low-resistance film. A nitride sidewall is formed to cover at least the side faces of an insulator cap and the upper electrode. A pad oxide film is formed to cover at least part of the side faces of the lower electrode and part of the upper surface of a semiconductor substrate. Since a second nitride sidewall is formed to cover the first nitride sidewall and the pad oxide film, a self-aligned contact hole can be formed by etching. As a result, a semiconductor device with a highly reliable self-aligned contact can be obtained.Type: GrantFiled: February 29, 2000Date of Patent: June 3, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takashi Uehara, Masato Kanazawa
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Patent number: 6100170Abstract: After forming a polysilicon film to be used as a gate electrode on a semiconductor substrate of silicon, an insulating thin film is deposited on the polysilicon film. Impurity ions are implanted into the polysilicon film through the insulating thin film, so as to form an amorphous layer on the surface of the polysilicon film. After removing the insulating thin film existing on the polysilicon film, a metal film is deposited on the amorphous layer. A reaction is caused between the amorphous layer and the metal film through annealing, so as to form a metal silicide layer on the surface of the polysilicon film.Type: GrantFiled: July 7, 1998Date of Patent: August 8, 2000Assignee: Matsushita Electronics CorporationInventors: Michikazu Matsumoto, Tatsuo Sugiyama, Shinichi Ogawa, Masato Kanazawa, Kouji Tamura, Masahiro Yasumi
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Patent number: 6055895Abstract: A slider of the punch carry out unit is moved in the X-axis direction adjacent a punching section of the punch press machine before or after a plate material is punched into a punched product by a punch press machine. At the same time, a gravity center and a shape of the punched product are calculated and recognized on the basis of the manufacturing data. On the basis of the obtained gravity center and the shape of the punched product, the gravity center of the punched product is moved under the lift arm by the X- and Y-axis locating mechanism. Vacuum pads located just over the punched product are selected or discriminated. Then, the lift arm is lowered and the punched product is held by actuating only the discriminated vacuum pads. During this lift motion, it is preferable to bend one end of the punched product slightly upward to easily separate the punched product from the remaining flat plate material.Type: GrantFiled: November 21, 1997Date of Patent: May 2, 2000Assignee: Amada America, Inc.Inventor: Masato Kanazawa
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Patent number: 5712194Abstract: A first interlayer dielectric film layer is formed on a P-type semiconductor substrate. First connection holes are formed at specified positions of the first interlayer dielectric film layer. A first conductive film layer is formed in a region including at least the first connection holes and is composed of three layers by sequentially laminating a barrier metal film, an aluminum alloy film, and an anti-reflection film. A second interlayer dielectric film layer is formed on the first conductive film layer and is composed of a lower layer of silicon oxide film, an intermediate layer of silicon oxide film made of inorganic silica or organic silica, and a upper layer of silicon oxide film. Specified positions of the second interlayer dielectric film layer are selectively removed to form second connection holes. A second conductive film layer is formed thereon and is composed of two layers of refractory metal film in the bottom layer and aluminum alloy film in the top layer.Type: GrantFiled: June 6, 1996Date of Patent: January 27, 1998Assignee: Matsushita Electronics CorporationInventor: Masato Kanazawa
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Patent number: 5459353Abstract: A first interlayer dielectric film layer is formed on a P-type semiconductor substrate. The first interlayer dielectric film is made of a BPSG film formed by the method of atmospheric pressure chemical vapor deposition. First connection holes are formed at specified positions of the first interlayer dielectric film layer. A first conductive film layer is formed in a region including at least the first connection holes. The first conductive film layer is composed of three layers by sequentially laminating a barrier metal film, an aluminum alloy film, and an anti-reflection film. On the first conductive film layer formed in a specified pattern, a second interlayer dielectric film layer is formed. The second interlayer dielectric film layer is composed of a lower layer of silicon oxide film, an intermediate layer of silicon oxide film made of inorganic silica or organic silica, and an upper layer of silicon oxide film. Specified positions of the second interlayer dielectric film layer are selectively removed.Type: GrantFiled: January 5, 1995Date of Patent: October 17, 1995Assignee: Matsushita Electronics CorporationInventor: Masato Kanazawa