Abstract: A data processing apparatus includes a first circuit unit operating with first clocks of a predetermined cycle, a second circuit unit operating with second clocks of a predetermined cycle different from the first clock cycle, and a first circuit block which generates and outputs a train of pulses in accordance with the first clock cycle.

Abstract: A method of controlling data transfer through a system bus between units in a computer system employs a split transfer technique that transfers data transfer requests separately from responses to the requests. The method provides one of the units with a bus grant signal to allow the unit to transfer a plurality of transferrable statuses to another unit that has requested them.

Abstract: A firmware modification system in a data processing apparatus, containing a processor for executing a program and a working program holding unit for holding therein data of the program executed by the processor. The system also includes fixed program data storing unit for storing a fixed program data and a modification data storing unit for storing modification data with which the fixed program data is to be modified, where the modification data storing unit is accessible from outside of the data processing apparatus for writing the modification data therein. A fixed program data loading unit is used for reading from the fixed program data storing unit, and loading the fixed program data in the working program holding unit to hold the fixed program data therein, and a working program modifying unit is used for modifying data of the program which is held in the working program holding unit, with the modification data stored in the modification data storing unit.