Patents by Inventor Masato Maede
Masato Maede has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9576947Abstract: In a semiconductor integrated circuit device, a plurality of electrode pads for external connection are arranged in a zigzag pattern. Some electrode pads of the electrode pads of the plurality of I/O cells which are closer to a side of the semiconductor chip, each have an end portion closer to the side of the semiconductor chip, the end portion being set at the same position as that of an end portion of the corresponding I/O cell. A power source-side protective circuit and a ground-side protective circuit against discharge of static electricity are provided with the power source-side protective circuit being closer to the scribe region. A distance between a center position of one of the electrode pads and the ground-side protective circuit of the corresponding I/O cell and a distance between a center position of the other one electrode pad and the ground-side protective circuit of the corresponding I/O cell are both short and are substantially equal between each I/O cell.Type: GrantFiled: May 5, 2016Date of Patent: February 21, 2017Assignee: SOCIONEXT INC.Inventors: Koichi Taniguchi, Masato Maede
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Publication number: 20160247796Abstract: In a semiconductor integrated circuit device, a plurality of electrode pads for external connection are arranged in a zigzag pattern. Some electrode pads of the electrode pads of the plurality of I/O cells which are closer to a side of the semiconductor chip, each have an end portion closer to the side of the semiconductor chip, the end portion being set at the same position as that of an end portion of the corresponding I/O cell. A power source-side protective circuit and a ground-side protective circuit against discharge of static electricity are provided with the power source-side protective circuit being closer to the scribe region. A distance between a center position of one of the electrode pads and the ground-side protective circuit of the corresponding I/O cell and a distance between a center position of the other one electrode pad and the ground-side protective circuit of the corresponding I/O cell are both short and are substantially equal between each I/O cell.Type: ApplicationFiled: May 5, 2016Publication date: August 25, 2016Inventors: Koichi TANIGUCHI, Masato MAEDE
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Patent number: 9379101Abstract: In a semiconductor integrated circuit device, a plurality of electrode pads for external connection are arranged in a zigzag pattern. Some electrode pads of the electrode pads of the plurality of I/O cells which are closer to a side of the semiconductor chip, each have an end portion closer to the side of the semiconductor chip, the end portion being set at the same position as that of an end portion of the corresponding I/O cell. A power source-side protective circuit and a ground-side protective circuit against discharge of static electricity are provided with the power source-side protective circuit being closer to the scribe region. A distance between a center position of one of the electrode pads and the ground-side protective circuit of the corresponding I/O cell and a distance between a center position of the other one electrode pad and the ground-side protective circuit of the corresponding I/O cell are both short and are substantially equal between each I/O cell.Type: GrantFiled: April 10, 2015Date of Patent: June 28, 2016Assignee: SOCIONEXT INCInventors: Koichi Taniguchi, Masato Maede
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Publication number: 20150214215Abstract: In a semiconductor integrated circuit device, a plurality of electrode pads for external connection are arranged in a zigzag pattern. Some electrode pads of the electrode pads of the plurality of I/O cells which are closer to a side of the semiconductor chip, each have an end portion closer to the side of the semiconductor chip, the end portion being set at the same position as that of an end portion of the corresponding I/O cell. A power source-side protective circuit and a ground-side protective circuit against discharge of static electricity are provided with the power source-side protective circuit being closer to the scribe region. A distance between a center position of one of the electrode pads and the ground-side protective circuit of the corresponding I/O cell and a distance between a center position of the other one electrode pad and the ground-side protective circuit of the corresponding I/O cell are both short and are substantially equal between each I/O cell.Type: ApplicationFiled: April 10, 2015Publication date: July 30, 2015Inventors: Koichi TANIGUCHI, Masato MAEDE
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Patent number: 9029917Abstract: In a semiconductor integrated circuit device, a plurality of electrode pads for external connection are arranged in a zigzag pattern. Some electrode pads of the electrode pads of the plurality of I/O cells which are closer to a side of the semiconductor chip, each have an end portion closer to the side of the semiconductor chip, the end portion being set at the same position as that of an end portion of the corresponding I/O cell. A power source-side protective circuit and a ground-side protective circuit against discharge of static electricity are provided with the power source-side protective circuit being closer to the scribe region. A distance between a center position of one of the electrode pads and the ground-side protective circuit of the corresponding I/O cell and a distance between a center position of the other one electrode pad and the ground-side protective circuit of the corresponding I/O cell are both short and are substantially equal between each I/O cell.Type: GrantFiled: May 13, 2014Date of Patent: May 12, 2015Assignee: Socionext Inc.Inventors: Koichi Taniguchi, Masato Maede
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Publication number: 20140246703Abstract: In a semiconductor integrated circuit device, a plurality of electrode pads for external connection are arranged in a zigzag pattern. Some electrode pads of the electrode pads of the plurality of I/O cells which are closer to a side of the semiconductor chip, each have an end portion closer to the side of the semiconductor chip, the end portion being set at the same position as that of an end portion of the corresponding I/O cell. A power source-side protective circuit and a ground-side protective circuit against discharge of static electricity are provided with the power source-side protective circuit being closer to the scribe region. A distance between a center position of one of the electrode pads and the ground-side protective circuit of the corresponding I/O cell and a distance between a center position of the other one electrode pad and the ground-side protective circuit of the corresponding I/O cell are both short and are substantially equal between each I/O cell.Type: ApplicationFiled: May 13, 2014Publication date: September 4, 2014Applicant: PANASONIC CORPORATIONInventors: Koichi TANIGUCHI, Masato MAEDE
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Patent number: 8759883Abstract: In a semiconductor integrated circuit device, a plurality of electrode pads for external connection are arranged in a zigzag pattern. Some electrode pads of the electrode pads of the plurality of I/O cells which are closer to a side of the semiconductor chip, each have an end portion closer to the side of the semiconductor chip, the end portion being set at the same position as that of an end portion of the corresponding I/O cell. A power source-side protective circuit and a ground-side protective circuit against discharge of static electricity are provided with the power source-side protective circuit being closer to the scribe region. A distance between a center position of one of the electrode pads and the ground-side protective circuit of the corresponding I/O cell and a distance between a center position of the other one electrode pad and the ground-side protective circuit of the corresponding I/O cell are both short and are substantially equal between each I/O cell.Type: GrantFiled: May 24, 2010Date of Patent: June 24, 2014Assignee: Panasonic CorporationInventors: Koichi Taniguchi, Masato Maede
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Patent number: 8395870Abstract: An output transistor bias generation circuit which applies a bias voltage to one of two NMOS transistors constituting an output circuit having a stack structure, includes diode-connected NMOS transistors provided between an external connection pad connected to an external signal line having a voltage higher than a power supply voltage of an LSI circuit, and the gate of an NMOS transistor, diode-connected NMOS transistors provided between the gate of the NMOS transistor and a ground line, a diode-connected NMOS transistor provided between the power supply line and the gate of the NMOS transistor, and a capacitor-connected NMOS transistor provided between the gate of the NMOS transistor and the ground line.Type: GrantFiled: November 4, 2011Date of Patent: March 12, 2013Assignee: Panasonic CorporationInventor: Masato Maede
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Patent number: 8154054Abstract: In a semiconductor chip in which external connection pads are arranged in three or more rows in a staggered configuration at the peripheral portion thereof, a first pad which is arranged in the outermost row is used as a power supply pad or a ground pad for an internal core circuit. To the first pad, a second pad which is arranged in the second outermost row is connected with a metal in the same layer as a pad metal. The resistance of a power supply line to the internal core circuit has a value of the parallel resistance of a resistance from the first pad and a resistance from the second pad, which is by far lower than the resistance from the first pad. Therefore, it is possible to prevent circuit misoperation resulting from an IR drop in the power supply of the internal core circuit.Type: GrantFiled: August 31, 2010Date of Patent: April 10, 2012Assignee: Panasonic CorporationInventor: Masato Maede
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Publication number: 20120049939Abstract: An output transistor bias generation circuit which applies a bias voltage to one of two NMOS transistors constituting an output circuit having a stack structure, includes diode-connected NMOS transistors provided between an external connection pad connected to an external signal line having a voltage higher than a power supply voltage of an LSI circuit, and the gate of an NMOS transistor, diode-connected NMOS transistors provided between the gate of the NMOS transistor and a ground line, a diode-connected NMOS transistor provided between the power supply line and the gate of the NMOS transistor, and a capacitor-connected NMOS transistor provided between the gate of the NMOS transistor and the ground line.Type: ApplicationFiled: November 4, 2011Publication date: March 1, 2012Applicant: PANASONIC CORPORATIONInventor: Masato MAEDE
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Patent number: 7940138Abstract: An oscillation circuit according to the present invention comprises a solid-state oscillator, an amplifier for feedback-controlling the solid-state oscillator, and ESD protecting circuits respectively connected to the input and output sides of the amplifier, wherein the ESD protecting circuit on the input side of the amplifier comprises an ESD protecting element whose constituent is a diode having a P-type diffusion layer and an N-type diffusion layer, and the ESD protecting circuit on the output side of the amplifier comprises an ESD protecting element whose constituent is an MOS transistor.Type: GrantFiled: February 4, 2010Date of Patent: May 10, 2011Assignee: Panasonic CorporationInventor: Masato Maede
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Publication number: 20100327324Abstract: In a semiconductor chip in which external connection pads are arranged in three or more rows in a staggered configuration at the peripheral portion thereof, a first pad which is arranged in the outermost row is used as a power supply pad or a ground pad for an internal core circuit. To the first pad, a second pad which is arranged in the second outermost row is connected with a metal in the same layer as a pad metal. The resistance of a power supply line to the internal core circuit has a value of the parallel resistance of a resistance from the first pad and a resistance from the second pad, which is by far lower than the resistance from the first pad. Therefore, it is possible to prevent circuit misoperation resulting from an IR drop in the power supply of the internal core circuit.Type: ApplicationFiled: August 31, 2010Publication date: December 30, 2010Applicant: PANASONIC CORPORATIONInventor: Masato Maede
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Patent number: 7816708Abstract: In a semiconductor chip in which external connection pads are arranged in three or more rows in a staggered configuration at the peripheral portion thereof, a first pad which is arranged in the outermost row is used as a power supply pad or a ground pad for an internal core circuit. To the first pad, a second pad which is arranged in the second outermost row is connected with a metal in the same layer as a pad metal. The resistance of a power supply line to the internal core circuit has a value of the parallel resistance of a resistance from the first pad and a resistance from the second pad, which is by far lower than the resistance from the first pad. Therefore, it is possible to prevent circuit misoperation resulting from an IR drop in the power supply of the internal core circuit.Type: GrantFiled: November 11, 2008Date of Patent: October 19, 2010Assignee: Panasonic CorporationInventor: Masato Maede
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Publication number: 20100230725Abstract: In a semiconductor integrated circuit device, a plurality of electrode pads for external connection are arranged in a zigzag pattern. Some electrode pads of the electrode pads of the plurality of I/O cells which are closer to a side of the semiconductor chip, each have an end portion closer to the side of the semiconductor chip, the end portion being set at the same position as that of an end portion of the corresponding I/O cell. A power source-side protective circuit and a ground-side protective circuit against discharge of static electricity are provided with the power source-side protective circuit being closer to the scribe region. A distance between a center position of one of the electrode pads and the ground-side protective circuit of the corresponding I/O cell and a distance between a center position of the other one electrode pad and the ground-side protective circuit of the corresponding I/O cell are both short and are substantially equal between each I/O cell.Type: ApplicationFiled: May 24, 2010Publication date: September 16, 2010Applicant: Panasonic CorporationInventors: Koichi TANIGUCHI, Masato Maede
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Patent number: 7768308Abstract: In a level shift circuit, the threshold voltage of N-type high-voltage transistors, to whose gates the voltage of a low-voltage supply VDD is applied, is set low. An input signal IN powered by the low-voltage supply VDD is input to the gate of an N-type transistor by way of an inverter. Therefore, even if the potentials at nodes W3 and W4 exceed the voltage of the low-voltage supply VDD, reverse current flow from the nodes W3 and W4 via parasitic diodes within the inverters into the low-voltage supply VDD is prevented. A protection circuit, composed of N-type transistor whose respective gates are fixed to the low-voltage supply VDD, is disposed between the two N-type high-voltage transistors N5, N6 and two N-type low-voltage transistors N1, N2 for receiving the complementary signals IN and XIN, thereby preventing the breakdown of those N-type complementary-signal-receiving transistors.Type: GrantFiled: June 4, 2008Date of Patent: August 3, 2010Assignee: Panasonic CorporationInventors: Masato Maede, Naoki Nojiri, Masahiro Gion, Shinji Kinuyama, Daisuke Matsuoka, Shiro Usami
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Patent number: 7750373Abstract: In a semiconductor integrated circuit device, a plurality of electrode pads for external connection are arranged in a zigzag pattern. Some electrode pads of the electrode pads of the plurality of I/O cells which are closer to a side of the semiconductor chip, each have an end portion closer to the side of the semiconductor chip, the end portion being set at the same position as that of an end portion of the corresponding I/O cell. A power source-side protective circuit and a ground-side protective circuit against discharge of static electricity are provided with the power source-side protective circuit being closer to the scribe region. A distance between a center position of one of the electrode pads and the ground-side protective circuit of the corresponding I/O cell and a distance between a center position of the other one electrode pad and the ground-side protective circuit of the corresponding I/O cell are both short and are substantially equal between each I/O cell.Type: GrantFiled: December 28, 2007Date of Patent: July 6, 2010Assignee: Panasonic CorporationInventors: Koichi Taniguchi, Masato Maede
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Publication number: 20100134193Abstract: An oscillation circuit according to the present invention comprises a solid-state oscillator, an amplifier for feedback-controlling the solid-state oscillator, and ESD protecting circuits respectively connected to the input and output sides of the amplifier, wherein the ESD protecting circuit on the input side of the amplifier comprises an ESD protecting element whose constituent is a diode having a P-type diffusion layer and an N-type diffusion layer, and the ESD protecting circuit on the output side of the amplifier comprises an ESD protecting element whose constituent is an MOS transistor.Type: ApplicationFiled: February 4, 2010Publication date: June 3, 2010Applicant: Panasonic Corporation LLPInventor: Masato MAEDE
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Patent number: 7683728Abstract: An oscillation circuit according to the present invention comprises a solid-state oscillator, an amplifier for feedback-controlling the solid-state oscillator, and ESD protecting circuits respectively connected to the input and output sides of the amplifier, wherein the ESD protecting circuit on the input side of the amplifier comprises an ESD protecting element whose constituent is a diode having a P-type diffusion layer and an N-type diffusion layer, and the ESD protecting circuit on the output side of the amplifier comprises an ESD protecting element whose constituent is an MOS transistor.Type: GrantFiled: November 16, 2007Date of Patent: March 23, 2010Assignee: Panasonic CorporationInventor: Masato Maede
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Publication number: 20090166620Abstract: In a semiconductor chip in which external connection pads are arranged in three or more rows in a staggered configuration at the peripheral portion thereof, a first pad which is arranged in the outermost row is used as a power supply pad or a ground pad for an internal core circuit. To the first pad, a second pad which is arranged in the second outermost row is connected with a metal in the same layer as a pad metal. The resistance of a power supply line to the internal core circuit has a value of the parallel resistance of a resistance from the first pad and a resistance from the second pad, which is by far lower than the resistance from the first pad. Therefore, it is possible to prevent circuit misoperation resulting from an IR drop in the power supply of the internal core circuit.Type: ApplicationFiled: November 11, 2008Publication date: July 2, 2009Inventor: Masato MAEDE
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Publication number: 20080238481Abstract: In a level shift circuit, the threshold voltage of N-type high-voltage transistors, to whose gates the voltage of a low-voltage supply VDD is applied, is set low. An input signal IN powered by the low-voltage supply VDD is input to the gate of an N-type transistor by way of an inverter. Therefore, even if the potentials at nodes W3 and W4 exceed the voltage of the low-voltage supply VDD, reverse current flow from the nodes W3 and W4 via parasitic diodes within the inverters into the low-voltage supply VDD is prevented. A protection circuit, composed of N-type transistor whose respective gates are fixed to the low-voltage supply VDD, is disposed between the two N-type high-voltage transistors N5, N6 and two N-type low-voltage transistors N1, N2 for receiving the complementary signals IN and XIN, thereby preventing the breakdown of those N-type complementary-signal-receiving transistors.Type: ApplicationFiled: June 4, 2008Publication date: October 2, 2008Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Masato MAEDE, Naoki Nojiri, Masahiro Gion, Shinji Kinuyama, Daisuke Matsuoka, Shiro Usami