Patents by Inventor Masato Matsumiya
Masato Matsumiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8687456Abstract: A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.Type: GrantFiled: August 31, 2012Date of Patent: April 1, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Ayako Sato, Masato Matsumiya
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Publication number: 20130205100Abstract: A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.Type: ApplicationFiled: August 31, 2012Publication date: August 8, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Ayako Sato, Masato Matsumiya
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Publication number: 20110141795Abstract: A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.Type: ApplicationFiled: February 18, 2011Publication date: June 16, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Yasurou MATSUZAKI, Takaaki SUZUKI, Masafumi YAMAZAKI, Kenichi KAWASAKI, Shinnosuke KAMATA, Ayako SATO, Masato MATSUMIYA
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Patent number: 7911825Abstract: A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.Type: GrantFiled: August 30, 2006Date of Patent: March 22, 2011Assignee: Fujitsu Semiconductor Ltd.Inventors: Yasurou Matsuzaki, Takaaki Suzuki, Masafumi Yamazaki, Kenichi Kawasaki, Shinnosuke Kamata, Ayako Sato, Masato Matsumiya
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Publication number: 20100321983Abstract: A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array.Type: ApplicationFiled: March 5, 2010Publication date: December 23, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Masato Takita, Masato Matsumiya, Satoshi Eto, Toshikazu Nakamura, Masatomo Hasegawa, Ayako Kitamoto, Kuninori Kawabata, Hideki Kanou, Toru Koga, Yuki Ishii, Shinichi Yamada, Kaoru Mori
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Publication number: 20100220540Abstract: A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array.Type: ApplicationFiled: March 5, 2010Publication date: September 2, 2010Applicant: FUJISU MICROELECTRONICS LIMITEDInventors: Masato Takita, Masato Matsumiya, Satoshi Eto, Toshikazu Nakamura, Masatomo Hasegawa, Ayako Kitamoto, Kuninori Kawabata, Hideki Kanou, Toru Koga, Yuki Ishii, Shinichi Yamada, Kaoru Mori
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Patent number: 7706209Abstract: A semiconductor device, including a word line driver for driving a word line connected to a memory cell in a memory cell array and for resetting the word line when the memory cell changes from an activated to a standby state. The reset level of the word line driver is set when resetting of the word line is performed, and may be switched between first and second potentials. A word line reset level generating circuit varies the amount of negative potential current supply in accordance with memory cell array operating conditions. The semiconductor device includes a plurality of power source circuits, each having an oscillation circuit and a capacitor, for driving the capacitor via an oscillation signal outputted by the oscillation circuit. At least some power source circuits share a common oscillation circuit, and different capacitors are driven via the common oscillation signal.Type: GrantFiled: December 22, 2005Date of Patent: April 27, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Masato Takita, Masato Matsumiya, Satoshi Eto, Toshikazu Nakamura, Masatomo Hasegawa, Ayako Kitamoto, Kuninori Kawabata, Hideki Kanou, Toru Koga, Yuki Ishii, Shinichi Yamada, Kaoru Mori
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Patent number: 7459960Abstract: It is intended to provide a semiconductor integrated circuit device and adjustment method of the same semiconductor integrated circuit device, capable of adjusting an analog signal outputted from an incorporated analog signal generating section without outputting it outside as an analog value. An analog signal AOUT is outputted from an analog signal generating section 3 in which an adjustment signal AD is inputted. The analog signal AOUT is inputted to a judgment section 1, in which it is compared and judged with a predetermined value and then a judgment signal JG is outputted. The judgment signal JG acts on a predetermined signal storing section 4 as an internal signal and the adjustment signal AD is fetched into the predetermined signal storing section 4. Further, the judgment signal JG is outputted as digital signal through an external terminal T2 and an external tester device acquires the adjustment signal and stores the acquired adjustment signal in the predetermined signal storing section 4.Type: GrantFiled: June 1, 2006Date of Patent: December 2, 2008Assignee: Fujitsu LimitedInventors: Yasushige Ogawa, Yoshiyuki Ishida, Masato Matsumiya
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Patent number: 7325173Abstract: During a first data compression test mode which disables an error correction function, first test data are written to a first regular memory block. Second test data are written to not only a second regular memory block, but a parity memory block. By changing the number of bits distributed to the first and second test data (compression rate of data), a data compression test for a parity memory block can be performed without need to increase the number of test terminals. As a result, the test time can be decreased and the test cost can be decreased.Type: GrantFiled: March 30, 2005Date of Patent: January 29, 2008Assignee: Fujitsu LimitedInventors: Akira Kikutake, Masato Matsumiya, Yasuhiro Onishi
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Patent number: 7297996Abstract: A twin-cell type semiconductor memory device in which the area of a chip can be reduced. In the twin-cell type semiconductor memory device for storing data in at least one pair of memory cells as complementary information, memory cells are arranged at each of a plurality of word lines at intervals at which bit lines are located. At least the one pair of memory cells, which have stored the complementary information and which indicate a plurality of areas each connected to a pair of bit lines, form a twin cell.Type: GrantFiled: December 12, 2005Date of Patent: November 20, 2007Assignee: Fujitsu LimitedInventors: Ayako Sato, Masato Matsumiya, Satoshi Eto
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Patent number: 7281155Abstract: A semiconductor memory device having a shift redundancy function includes a switch circuit for changeably connecting a plurality of decode signal lines decoding an address signal to a plurality of selecting lines and redundancy selecting lines, and executes a switch operation for shifting at least one of a plurality of decode lines in the direction of a first redundancy selecting line positioned at one of the ends among a plurality of selecting lines or a second switch operation for shifting at least one of the decode lines in the direction of a second redundancy selecting line positioned at the other end among the selecting lines or both of the first and second operations when any fault occurs in a plurality of selecting lines.Type: GrantFiled: July 22, 1999Date of Patent: October 9, 2007Assignee: Fujitsu LimitedInventors: Satoshi Eto, Masato Matsumiya, Toshimi Ikeda, Yuki Ishii, Akira Kikutake, Kuninori Kawabata
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Publication number: 20060294322Abstract: A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.Type: ApplicationFiled: August 30, 2006Publication date: December 28, 2006Inventors: Yasurou Matsuzaki, Takaaki Suzuki, Masafumi Yamazaki, Kenichi Kawasaki, Shinnosuke Kamata, Ayako Sato, Masato Matsumiya
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Patent number: 7152150Abstract: A semiconductor memory device includes a memory core circuit, a command circuit which receives commands from an exterior of the device at intervals at least as long as a minimum command cycle, a timing generator configured to request a read access to the memory core circuit immediately after inputting of a read command if a command supplied from the exterior to the command circuit is the read command, to perform a read operation on the memory core circuit immediately after the request of the read access if there is no currently performed operation in the memory core circuit, to request a write access to the memory core circuit after data is fixed prior to an end of a command cycle during which a write command corresponding to the write access is entered from the exterior to the command circuit, to perform a write operation on the memory core circuit immediately after the request of the write access if there is no currently performed operation in the memory core circuit, and to control an order of a pluralityType: GrantFiled: July 29, 2002Date of Patent: December 19, 2006Assignee: Fujitsu LimitedInventors: Ayako Sato, Masato Matsumiya
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Patent number: 7120761Abstract: A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.Type: GrantFiled: October 31, 2002Date of Patent: October 10, 2006Assignee: Fujitsu LimitedInventors: Yasurou Matsuzaki, Takaaki Suzuki, Masafumi Yamazaki, Kenichi Kawasaki, Shinnosuke Kamata, Ayako Sato, Masato Matsumiya
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Publication number: 20060214724Abstract: It is intended to provide a semiconductor integrated circuit device and adjustment method of the same semiconductor integrated circuit device, capable of adjusting an analog signal outputted from an incorporated analog signal generating section without outputting it outside as an analog value. An analog signal AOUT is outputted from an analog signal generating section 3 in which an adjustment signal AD is inputted. The analog signal AOUT is inputted to a judgment section 1, in which it is compared and judged with a predetermined value and then a judgment signal JG is outputted. The judgment signal JG acts on a predetermined signal storing section 4 as an internal signal and the adjustment signal AD is fetched into the predetermined signal storing section 4. Further, the judgment signal JG is outputted as digital signal through an external terminal T2 and an external tester device acquires the adjustment signal and stores the acquired adjustment signal in the predetermined signal storing section 4.Type: ApplicationFiled: June 1, 2006Publication date: September 28, 2006Applicant: FUJITSU LIMITEDInventors: Yasushige Ogawa, Yoshiyuki Ishida, Masato Matsumiya
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Patent number: 7079443Abstract: A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array.Type: GrantFiled: August 1, 2003Date of Patent: July 18, 2006Assignee: Fujitsu LimitedInventors: Masato Takita, Masato Matsumiya, Satoshi Eto, Toshikazu Nakamura, Masatomo Hasegawa, Ayako Kitamoto, Kuninori Kawabata, Hideki Kanou, Toru Koga, Yuki Ishii, Shinichi Yamada, Kaoru Mori
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Publication number: 20060156213Abstract: During a first data compression test mode which disables an error correction function, first test data are written to a first regular memory block. Second test data are written to not only a second regular memory block, but a parity memory block. By changing the number of bits distributed to the first and second test data (compression rate of data), a data compression test for a parity memory block can be performed without need to increase the number of test terminals. As a result, the test time can be decreased and the test cost can be decreased.Type: ApplicationFiled: March 30, 2005Publication date: July 13, 2006Inventors: Akira Kikutake, Masato Matsumiya, Yasuhiro Onishi
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Publication number: 20060098523Abstract: A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array.Type: ApplicationFiled: December 22, 2005Publication date: May 11, 2006Inventors: Masato Takita, Masato Matsumiya, Satoshi Eto, Toshikazu Nakamura, Masatomo Hasegawa, Ayako Kitamoto, Kuninori Kawabata, Hideki Kanou, Toru Koga, Yuki Ishii, Shinichi Yamada, Kaoru Mori
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Publication number: 20060086951Abstract: A twin-cell type semiconductor memory device in which the area of a chip can be reduced. In the twin-cell type semiconductor memory device for storing data in at least one pair of memory cells as complementary information, memory cells are arranged at each of a plurality of word lines at intervals at which bit lines are located. At least the one pair of memory cells, which have stored the complementary information and which indicate a plurality of areas each connected to a pair of bit lines, form a twin cell.Type: ApplicationFiled: December 12, 2005Publication date: April 27, 2006Inventors: Ayako Sato, Masato Matsumiya, Satoshi Eto
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Patent number: 7005693Abstract: A twin-cell type semiconductor memory device in which the area of a chip can be reduced. In the twin-cell type semiconductor memory device for storing data in at least one pair of memory cells as complementary information, memory cells are arranged at each of a plurality of word lines at intervals at which bit lines are located. At least the one pair of memory cells, which have stored the complementary information and which indicate a plurality of areas each connected to a pair of bit lines, form a twin cell.Type: GrantFiled: September 3, 2003Date of Patent: February 28, 2006Assignee: Fujitsu LimitedInventors: Ayako Sato, Masato Matsumiya, Satoshi Eto