Patents by Inventor Masato Matsushima

Masato Matsushima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240179254
    Abstract: An image forming apparatus that utilizes a communication device is disclosed. A communication unit of a housing which corresponds to an antenna portion is provided at a position at which the communication unit can be seen without obstruction from the upper side. A communication device such as a smartphone can be brought close to or into contact with the communication unit readily. Accordingly, wireless communication between the antenna portion and the communication device can be established.
    Type: Application
    Filed: October 5, 2023
    Publication date: May 30, 2024
    Inventors: Ryoichi Matsushima, Hirofumi Kondo, Yasuhiro Kato, Masayoshi Hayashi, Masato Sueyasu, Reiko Toyama
  • Patent number: 11971978
    Abstract: A vehicle network system employing a controller area network protocol includes a bus, a first electronic control unit, and a second electronic control unit. The first electronic control unit transmits, via the bus, at least one data frame including an identifier relating to data used for a calculation for obtaining a message authentication code indicating authenticity of transmission content. The second electronic control unit receives the at least one data frame transmitted vis the bus and verifies the message authentication code in accordance with the identifier included in the at least one data frame.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: April 30, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Yoshihiro Ujiie, Masato Tanabe, Takeshi Kishikawa, Tomoyuki Haga, Hideki Matsushima
  • Patent number: 11943233
    Abstract: An electronic control unit is connected to a network in an in-vehicle network system. The electronic control unit includes a first control circuit and a second control circuit. The first control circuit is connected to the network via the second control circuit. The second control circuit performs a first determination process on a frame to determine conformity of the frame with a first rule. Upon determining that the frame conforms to the first rule, the second control circuit transmits the frame to the first control circuit. The first control circuit performs a second determination process on the frame to determine conformity of the frame with a second rule. The second rule is different from the first rule.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: March 26, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Yoshihiro Ujiie, Jun Anzai, Yoshihiko Kitamura, Masato Tanabe, Hideki Matsushima, Tomoyuki Haga, Takeshi Kishikawa, Ryota Sugiyama
  • Patent number: 6387722
    Abstract: The present invention provides an epitaxial wafer comprising a (111) substrate of a semiconductor having cubic crystal structure, a first GaN layer having a thickness of 60 nanometers or more, a second GaN layer having a thickness of 0.1 &mgr;m or more and a method for preparing it.
    Type: Grant
    Filed: May 26, 2000
    Date of Patent: May 14, 2002
    Assignee: Sumitomo Electric Industries, LTD
    Inventors: Kensaku Motoki, Masato Matsushima, Katsushi Akita, Mitsuru Shimazu, Kikurou Takemoto, Hisashi Seki, Akinori Koukitu
  • Publication number: 20020011599
    Abstract: An n-type GaN substrate having a safe n-type dopant instead of Si which is introduced by perilous silane gas. The safe n-dopant is oxygen. An oxygen doped n-type GaN free-standing crystal is made by forming a mask on a GaAs substrate, making apertures on the mask for revealing the undercoat GaAs, growing GaN films through the apertures of the mask epitaxially on the GaAs substrate from a material gas including oxygen, further growing the GaN film also upon the mask for covering the mask, eliminating the GaAs substrate and the mask, and isolating a freestanding GaN single crystal. The GaN is an n-type crystal having carriers in proportion to the oxygen concentration.
    Type: Application
    Filed: May 27, 1999
    Publication date: January 31, 2002
    Inventors: KENSAKU MOTOKI, TAKUJI OKAHISA, NAOKI MATSUMOTO, MASATO MATSUSHIMA
  • Patent number: 6270587
    Abstract: The present invention provides an epitaxial wafer comprising a (111) substrate of a semiconductor having cubic crystal structure, a first GaN layer having a thickness of 60 nanometers or more, a second GaN layer having a thickness of 0.1 &mgr;m or more and a method for preparing it.
    Type: Grant
    Filed: March 12, 1998
    Date of Patent: August 7, 2001
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kensaku Motoki, Masato Matsushima, Katsushi Akita, Mitsuru Shimazu, Kikurou Takemoto, Hisashi Seki, Akinori Koukitu
  • Patent number: 6031252
    Abstract: An epitaxial wafer enabling epitaxial growth at a high temperature includes a compound semiconductor substrate containing As or P, and a covering layer including GaN; or InN; or AlN; or a nitride mixed-crystalline material containing Al, Ga, In and N. The covering layer covers at least a front surface and a back surface of the substrate. A method of preparing such an epitaxial wafer including steps of growing the covering layer at a growth temperature of at least 300.degree. C. and less than 800.degree. C. so as to cover at least the front and back surfaces of the substrate, and then annealing the substrate having the covering thereon layer at a temperature of at least 700.degree. C. and less than 1200.degree. C.
    Type: Grant
    Filed: August 29, 1996
    Date of Patent: February 29, 2000
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yoshiki Miura, Mitsuru Shimazu, Kensaku Motoki, Takuji Okahisa, Masato Matsushima, Hisashi Seki, Akinori Koukitu
  • Patent number: 5970314
    Abstract: A process for forming a high quality epitaxial compound semiconductor layer of indium gallium nitride In.sub.x Ga.sub.1-x N, (where 0<x<1) on a substrate. A first gas including indium trichloride (InCl.sub.3) and a second gas including ammonia (NH.sub.3) are introduced into a reaction chamber and heated at a first temperature. Indium nitride (InN) is grown epitaxially on the substrate by nitrogen (N.sub.2) carrier gas to form an InN buffer layer. Thereafter, a third gas including hydrogen chloride (H1) and gallium (Ga) is introduced with the first and second gases into a chamber heated at a second temperature higher than the first temperature and an epitaxial In.sub.x Ga.sub.1-x N layer is grown on the buffer layer by N.sub.2 gas. By using helium, instead of N.sub.2, as carrier gas, the In.sub.x Ga.sub.1-x N layer with more homogeneous quality is obtained. In addition, the InN buffer layer is allowed to be modified into a GaN buffer layer.
    Type: Grant
    Filed: March 24, 1997
    Date of Patent: October 19, 1999
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takuji Okahisa, Mitsuru Shimazu, Masato Matsushima, Yoshiki Miura, Kensaku Motoki, Hisashi Seki, Akinori Koukitu
  • Patent number: 5843590
    Abstract: A high performance epitaxial wafer which is useful, for example in a light emitting device is produced with a buffer layer. The epitaxial wafer has a substrate of a compound semiconductor selected from a group consisting of GaAs, GaP, InAs and InP. The buffer layer of GaN is grown on the substrate to a thickness within the range of 10 nm to 80 nm. An epitaxial layer of GaN is formed on the buffer layer. The buffer layer is grown at a first temperature by organic metal chloride vapor phase epitaxy, while the epitaxial layer is grown at a second temperature, which is higher than the first temperature, by the organic metal chloride vapor phase epitaxy.
    Type: Grant
    Filed: December 19, 1995
    Date of Patent: December 1, 1998
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yoshiki Miura, Keiichiro Fujita, Kikurou Takemoto, Masato Matsushima, Hideki Matsubara, Shigenori Takagishi, Hisashi Seki, Akinori Koukitu
  • Patent number: 5756374
    Abstract: A compound semiconductor light emitting device of high performance and a method which can industrially prepare the same are provided. The compound semiconductor light emitting device includes a GaAs substrate, a buffer layer consisting of GaN, having a thickness of 10 nm to 80 nm, which is formed on the substrate, an epitaxial layer consisting of Al.sub.x Ga.sub.1-x N(0.ltoreq.x<1) which is formed on the buffer layer, an incommensurate plane which is located on the interface between the buffer layer and the epitaxial layer, a light emitting layer which is formed on the epitaxial layer, and a cladding layer which is formed on the light emitting layer. The buffer layer is formed by organic metal chloride vapor phase epitaxy at a first temperature, while the epitaxial layer is formed by organic metal chloride vapor phase epitaxy at a second temperature which is higher than the first temperature. The light emitting layer preferably consists of In.sub.y Ga.sub.1-y N (0<y<1) which is doped with Mg.
    Type: Grant
    Filed: May 15, 1997
    Date of Patent: May 26, 1998
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yoshiki Miura, Hideki Matsubara, Masato Matsushima, Hisashi Seki, Akinori Koukitu
  • Patent number: 5665986
    Abstract: A compound semiconductor light emitting device of high performance and a method which can industrially prepare the same are provided. The compound semiconductor light emitting device includes a GaAs substrate, a buffer layer consisting of GaN, having a thickness of 10 nm to 80 nm, which is formed on the substrate, an epitaxial layer consisting of Al.sub.x Ga.sub.1-x N (0.ltoreq.x<1) which is formed on the buffer layer, an incommensurate plane which is located on the interface between the buffer layer and the epitaxial layer, a light emiting layer which is formed on the epitaxial layer, and a cladding layer which is formed on the light emitting layer. The buffer layer is formed by organic metal chloride vapor phase epitaxy at a first temperature, while the epitaxial layer is formed by organic metal chloride vapor phase epitaxy at a second temperature which is higher than the first temperature. The light emitting layer preferably consists of In.sub.y Ga.sub.1-y N (0<y<1) which is doped with Mg.
    Type: Grant
    Filed: March 7, 1996
    Date of Patent: September 9, 1997
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yoshiki Miura, Hideki Matsubara, Masato Matsushima, Hisashi Seki, Akinori Koukitu