Abstract: A semiconductor device includes a base member and a first semiconductor chip mounted over the base member. The first semiconductor chip including a first circuit, a second circuit, and a third circuit arranged between the first circuit and the second circuit and a plurality of pads. The first, second and third circuits are arranged along a first side of the first semiconductor chip. In plan view, the pads are located outside of the circuits and include a plurality of first pads arranged at a first pitch, and a plurality of second pads arranged at the first pitch. A distance between a first pad group comprised of the first pads and a second pad group comprised of the second pads is larger than the first pitch. Further, in a plan view, a part of the third circuit is located between the first pad group and the second pad group.

Abstract: In a QFN that includes a die pad, a semiconductor chip mounted on the die pad, a plurality of leads arranged around the semiconductor chip, a plurality of wires that electrically connect the plurality of electrode pads of the semiconductor chip with the plurality of leads, respectively, and a sealing member sealing the semiconductor chip and the plurality of wires, first and second step portions are formed at shifted positions on the left and right sides of each of the leads to make the positions of the first and second step portions shifted between the adjacent leads. As a result, the gap between the leads is narrowed, thereby achieving the miniaturization or the increase in the number of pins of the QFN.

Abstract: A semiconductor device includes a base member and a first semiconductor chip mounted over the base member. The first semiconductor chip including a first circuit, a second circuit, and a third circuit arranged between the first circuit and the second circuit and a plurality of pads. The first, second and third circuits are arranged along a first side of the first semiconductor chip. In plan view, the pads are located outside of the circuits and include a plurality of first pads arranged at a first pitch, and a plurality of second pads arranged at the first pitch. A distance between a first pad group comprised of the first pads and a second pad group comprised of the second pads is larger than the first pitch. Further, in a plan view, a part of the third circuit is located between the first pad group and the second pad group.

Abstract: A semiconductor device includes a base member and a first semiconductor chip mounted over the base member. The first semiconductor chip including a first circuit, a second circuit, and a third circuit arranged between the first circuit and the second circuit and a plurality of pads. The first, second and third circuits are arranged along a first side of the first semiconductor chip. In plan view, the pads are located outside of the circuits and include a plurality of first pads arranged at a first pitch, and a plurality of second pads arranged at the first pitch. A distance between a first pad group comprised of the first pads and a second pad group comprised of the second pads is larger than the first pitch. Further, in a plan view, a part of the third circuit is located between the first pad group and the second pad group.

Abstract: In a QFN that includes a die pad, a semiconductor chip mounted on the die pad, a plurality of leads arranged around the semiconductor chip, a plurality of wires that electrically connect the plurality of electrode pads of the semiconductor chip with the plurality of leads, respectively, and a sealing member sealing the semiconductor chip and the plurality of wires, first and second step portions are formed at shifted positions on the left and right sides of each of the leads to make the positions of the first and second step portions shifted between the adjacent leads. As a result, the gap between the leads is narrowed, thereby achieving the miniaturization or the increase in the number of pins of the QFN.

Abstract: A semiconductor device includes a base member and a first semiconductor chip mounted over the base member. The first semiconductor chip including a first circuit, a second circuit, and a third circuit arranged between the first circuit and the second circuit and a plurality of pads. The first, second and third circuits are arranged along a first side of the first semiconductor chip. In plan view, the pads are located outside of the circuits and include a plurality of first pads arranged at a first pitch, and a plurality of second pads arranged at the first pitch. A distance between a first pad group comprised of the first pads and a second pad group comprised of the second pads is larger than the first pitch. Further, in a plan view, a part of the third circuit is located between the first pad group and the second pad group.

Abstract: In a QFN that includes a die pad, a semiconductor chip mounted on the die pad, a plurality of leads arranged around the semiconductor chip, a plurality of wires that electrically connect the plurality of electrode pads of the semiconductor chip with the plurality of leads, respectively, and a sealing member sealing the semiconductor chip and the plurality of wires, first and second step portions are formed at shifted positions on the left and right sides of each of the leads to make the positions of the first and second step portions shifted between the adjacent leads. As a result, the gap between the leads is narrowed, thereby achieving the miniaturization or the increase in the number of pins of the QFN.

Abstract: The formation of a void is suppressed in the assembly of a semiconductor device. An MCU chip and an AFE chip are mounted over a die pad formed of a quadrangle having a pair of first sides and a pair of second sides. After wire bonding is carried out on the MCU chip and the AFE chip, resin is supplied from the side of one second side of the two second sides to the side of the other second side. The resin is thereby passed through the opening between a first pad group and a second pad group over the MCU chip to fill the area between the chips and thus the formation of a void is suppressed in the area between the chips.

Abstract: The formation of a void is suppressed in the assembly of a semiconductor device. An MCU chip and an AFE chip are mounted over a die pad formed of a quadrangle having a pair of first sides and a pair of second sides. After wire bonding is carried out on the MCU chip and the AFE chip, resin is supplied from the side of one second side of the two second sides to the side of the other second side. The resin is thereby passed through the opening between a first pad group and a second pad group over the MCU chip to fill the area between the chips and thus the formation of a void is suppressed in the area between the chips.

Abstract: The present invention enhances the processing efficiency of assembling of a semiconductor device. After performing resin molding by a through-gate method, the package dicing is performed such that leads and inclined portions of sealing bodies are cut while adhering a dicing tape to front surfaces of a plurality of sealing bodies. Thereafter, in a state that the plurality of sealing bodies are fixed to the dicing tape, probes are brought into contact with external terminals so as to perform a selection test whereby, after package dicing, it is possible to perform the test in a state that semiconductor devices are held on the dicing tape without accommodating the semiconductor devices in a tray. As a result, it is possible to enhance the processing efficiency of the assembling of a QFN (semiconductor device).

Abstract: A tray is constituted by a tray body portion for connecting a plurality of pockets and cushioning portions which are arranged on the bottom portions of the pockets serving as contact positions between the pockets and CSPs when the CSPs are stored in the pockets and which are formed of a soft material having a degree of hardness lower than that of the tray body portion. The tray moderates impact force acting on the CSPs in falling the tray to prevent the CSP from being broken and damaged.