Abstract: In one aspect, the present disclosure provides a microcontroller device that has, in one chip: a central processing unit; a plurality of peripheral circuits configured to execute respective prescribed processes in response to corresponding trigger signals; and a peripheral control unit that controls respective activations of the plurality of peripheral circuits, wherein at least one of the peripheral circuits is configured to: control operation of an external device; determine whether or not the operation of the external device has ended without an error; enter a standby mode to accept a next trigger signal when the operation of the external device ended without an error; and generate an interrupt signal to interrupt the central processing unit when the operation of the external device ended with an error.

Abstract: In one aspect, the present disclosure provides a microcontroller device that has, in one chip: a central processing unit; a plurality of peripheral circuits configured to execute respective prescribed processes in response to corresponding trigger signals; and a peripheral control unit that controls respective activations of the plurality of peripheral circuits, wherein at least one of the peripheral circuits is configured to: control operation of an external device; determine whether or not the operation of the external device has ended without an error; enter a standby mode to accept a next trigger signal when the operation of the external device ended without an error; and generate an interrupt signal to interrupt the central processing unit when the operation of the external device ended with an error.

Abstract: A microprocessor according to an aspect of the present invention includes an arithmetic operation unit. The arithmetic operation unit includes: a plurality of arithmetic operation devices arranged in a multi-stage arrangement; a delay device provided to each stage of the arithmetic operation devices excluding a final stage, and configured to delay an arithmetic operation result of the arithmetic operation devices for one cycle; and a selector provided to each stage of the arithmetic operation devices excluding the final stage, and configured to select either the arithmetic operation result of the arithmetic operation devices or the arithmetic operation result delayed for one cycle in the delay device and output the selected result to the arithmetic operation device in a next stage. The microprocessor is configured to collectively process a plurality of arithmetic operations from the arithmetic operation unit by controlling a selecting condition in the selector.

Abstract: Data output apparatus registers special format data added to specific character data together therewith in a registered word memory. When sentence data is read out from a sentence memory, the character data included in the sentence data and coinciding with the specific character data is automatically printed with the special format data.