Patents by Inventor Masato Sumikawa
Masato Sumikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130094245Abstract: Provided are a lighting apparatus capable of improving heat-releasing performance while maintaining structural strength, subduing luminance unevenness due to uneven heat distribution, and allowing the device to be thinner, and an image display apparatus including the lighting apparatus. A heat-conducting member (6) includes: a light-source supporter having a plane facing a light-incident plane; and a plate section having a plane facing a light-emitting plane and a plane facing a heat-releasing member (5), the light-source supporter being adjacent to the plate section. On the light-source supporter, a light source (7) is positioned on the plane facing the light-incident plane so as to face the light-incident plane, the plane of the plate section which faces the heat-releasing member (5) contacts a plane of the heat-releasing member (5) which faces a light guide member, and a centroid of the plate section deviates along a direction parallel to both the light-incident and light-emitting planes.Type: ApplicationFiled: February 4, 2011Publication date: April 18, 2013Applicant: Sharp Kabushiki KaishaInventors: Hirofumi Kanda, Masato Sumikawa, Takeshi Takayama, Koyu Sakai, Keiko Mori
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Patent number: 8068194Abstract: In the line light source device and the plane light emission device, first recesses 14 are formed between adjoining light emission elements 5, on surfaces of sealing resin layers 10 opposite to the board 4. The line light source device and the plane light emission device, in which the light emission elements are coated with resin, have a simple configuration and high uniformity in luminous intensity in an emission end face of the device.Type: GrantFiled: June 11, 2008Date of Patent: November 29, 2011Assignee: Sharp Kabushiki KaishaInventors: Shin Itoh, Masato Sumikawa, Yoshinobu Nakamura, Masahiro Ikehara, Tsukasa Inoguchi
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Patent number: 7995161Abstract: A surface light source includes a light source and an optical waveguide plate. The light source serves to emit light. The optical waveguide plate has an incident end face where the light is incident and a light exit surface where the light incident on the incident end face exits. Further, the optical waveguide plate has a refractive index n. The incident end face has a plurality of concave portions. The angle between a plane formed by the plurality of concave portions and a tangent plane of the incident end face is not more than (90?2·arcsin(1/n)) degree.Type: GrantFiled: December 18, 2008Date of Patent: August 9, 2011Assignee: Sharp Kabushiki KaishaInventors: Shin Ito, Masato Sumikawa, Yutaka Okada
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Patent number: 7692312Abstract: A semiconductor package providing with a printed circuit board and a semiconductor device, including a semiconductor substrate having a surface provided with an external connection electrode and mounted on the printed circuit board, and, a surface opposite that with said external connection electrode, abrased with a mirror finish and reinforced with a back-surface reinforcement.Type: GrantFiled: June 30, 2006Date of Patent: April 6, 2010Assignee: Sharp Kabushiki KaishaInventors: Masato Sumikawa, Kazumi Tanaka
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Publication number: 20090296017Abstract: In the line light source device and the plane light emission device, first recesses 14 are formed between adjoining light emission elements 5, on surfaces of sealing resin layers 10 opposite to the board 4. The line light source device and the plane light emission device, in which the light emission elements are coated with resin, have a simple configuration and high uniformity in luminous intensity in an emission end face of the device.Type: ApplicationFiled: June 11, 2008Publication date: December 3, 2009Applicant: SHARP KABUSHIKI KAISHAInventors: Shin Itoh, Masato Sumikawa, Yoshinobu Nakamura, Masahiro Ikehara, Tsukasa Inoguchi
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Publication number: 20090167989Abstract: A surface light source includes a light source and an optical waveguide plate. The light source serves to emit light. The optical waveguide plate has an incident end face where the light is incident and a light exit surface where the light incident on the incident end face exits. Further, the optical waveguide plate has a refractive index n. The incident end face has a plurality of concave portions. The angle between a plane formed by the plurality of concave portions and a tangent plane of the incident end face is not more than (90?2·arcsin(1/n)) degree.Type: ApplicationFiled: December 18, 2008Publication date: July 2, 2009Applicant: Sharp Kabushiki KaishaInventors: Shin ITO, Masato Sumikawa, Yutaka Okada
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Publication number: 20070084904Abstract: A conductive ball is formed by coating a generally spherical-shaped core made of a non-metallic material with a coating layer composed of a Cu layer and an Sn-5.5Ag alloy layer of non-eutectic composition. The conductive ball is disposed on a land of an electronic component via flux and reflown at heating temperatures whose peak temperatures reach 250 to 260° C. The Sn-5.5Ag alloy of non-eutectic composition is put in the state in which a solidus portion and a liquidus portion coexist to keep flowability relatively small. The conductive ball is fixed on the land without exposing an SnCu layer formed on the Cu layer. An electrode is formed without exposing the SnCu layer having relatively poor solder wettability. Between the electronic component and a circuit board, a joint section having a good electric conduction property and mechanical strength may be formed.Type: ApplicationFiled: May 24, 2004Publication date: April 19, 2007Applicants: SHARP KABUSHIKI KAISHA, SEKISUI CHEMICAL CO., LTD.Inventors: Masato Sumikawa, Rina Murayama, Masashi Ogawa, Kiyoto Matsushita
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Publication number: 20060249853Abstract: A semiconductor package providing with a printed circuit board and a semiconductor device, including a semiconductor substrate having a surface provided with an external connection electrode and mounted on the printed circuit board, and, a surface opposite that with said external connection electrode, abrased with a mirror finish and reinforced with a back-surface reinforcement.Type: ApplicationFiled: June 30, 2006Publication date: November 9, 2006Inventors: Masato Sumikawa, Kazumi Tanaka
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Patent number: 7038144Abstract: An electronic component having an electrode structure to increase an allowance positional deviation in a mounting process as well as a method and a structure for mounting a semiconductor device are provided. The semiconductor device includes, on electrodes, connection materials connecting the semiconductor device and a substrate. The connection materials include a composite connection material formed of a core and a conductor covering the core, the core having an a low modulus of elasticity at room temperature smaller than that of the conductor at room temperature, and a single-layer connection material formed of a conductor.Type: GrantFiled: November 8, 2001Date of Patent: May 2, 2006Assignee: Sharp Kabushiki KaishaInventors: Masao Yasuda, Masato Sumikawa
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Patent number: 6587353Abstract: In the semiconductor device, externally connecting electrodes are placed on a semiconductor substrate. A rewiring pattern for connecting each on-chip electrode to corresponding external connecting electrode is routed, in the vicinity of the externally connecting electrode, in a direction where the effect of strain after mounting of the semiconductor substrate is small. Specifically, the rewiring pattern is routed such that the routing direction will not match the direction coupling the center of the semiconductor substrate to the externally connecting electrode along which large thermal stress is expected. Accordingly, strain that will occur at the rewiring pattern after mounting the semiconductor substrate to the mounting board is reduced. Adverse effects of the strain stress can be prevented without widening the externally connecting interconnection.Type: GrantFiled: May 25, 2001Date of Patent: July 1, 2003Assignee: Sharp Kabushiki KaishaInventors: Masato Sumikawa, Kazumi Tanaka
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Patent number: 6441500Abstract: A semiconductor device having a plurality of externally connecting electrodes arranged on a semiconductor chip includes on-chip electrodes, resin members formed separately from each other and provided corresponding to the plurality of externally connecting electrodes, and interconnections connecting the corresponding on-chip electrode and the corresponding externally connecting electrode. Such separately formed resin members for the externally connecting electrodes allow relaxation of thermal stress produced in the externally connecting electrodes.Type: GrantFiled: September 12, 2000Date of Patent: August 27, 2002Assignee: Sharp Kabushiki KaishaInventors: Masato Sumikawa, Kazumi Tanaka, Tomotoshi Sato
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Publication number: 20020100610Abstract: An electronic component having an electrode structure to increase an allowance positional deviation in a mounting process as well as a method and a structure for mounting a semiconductor device are provided. The semiconductor device includes, on electrodes, connection materials connecting the semiconductor device and a substrate. The connection materials include a composite connection material formed of a core and a conductor covering the core, the core having an a low modulus of elasticity at room temperature smaller than that of the conductor at room temperature, and a single-layer connection material formed of a conductor.Type: ApplicationFiled: November 8, 2001Publication date: August 1, 2002Inventors: Masao Yasuda, Masato Sumikawa
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Patent number: 6362529Abstract: A stacked semiconductor device includes a plurality of stacked semiconductor chips, each of the semiconductor chips including a penetrating electrode which penetrates from a front surface to a back surface of the semiconductor chip, a first electrode formed on the front surface, a second electrode formed on the back surface and wiring patterns formed on the front and back surfaces for selectively connecting the first and second electrodes through the penetrating electrode, the first electrode of a lower semiconductor chip abutting the second electrode of an upper semiconductor chip with respect to adjacent two of the stacked semiconductor chips.Type: GrantFiled: September 22, 2000Date of Patent: March 26, 2002Assignee: Sharp Kabushiki KaishaInventors: Masato Sumikawa, Kazumi Tanaka
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Publication number: 20010045649Abstract: In the semiconductor device, externally connecting electrodes are placed on a semiconductor substrate. A rewiring pattern for connecting each on-chip electrode to corresponding external connecting electrode is routed, in the vicinity of the externally connecting electrode, in a direction where the effect of strain after mounting of the semiconductor substrate is small. Specifically, the rewiring pattern is routed such that the routing direction will not match the direction coupling the center of the semiconductor substrate to the externally connecting electrode along which large thermal stress is expected. Accordingly, strain that will occur at the rewiring pattern after mounting the semiconductor substrate to the mounting board is reduced. Adverse effects of the strain stress can be prevented without widening the externally connecting interconnection.Type: ApplicationFiled: May 25, 2001Publication date: November 29, 2001Inventors: Masato Sumikawa, Kazumi Tanaka
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Publication number: 20010033016Abstract: A semiconductor device is manufactured in a method including the steps of: abrasing a surface of a wafer opposite that thereof having a solder ball serving as an external connection electrode; and reinforcing the abrased surface with resin serving as a back-surface reinforcement member. More specifically, the resin is resin of rubber type, silicone type, epoxy type, polyimide type or urethane type. Preferably, previously grinding the surface to be abrased is previously ground to produce the device in a reduced process time. The structure can advantageously prevent a solder connection from breaking as an LSI chip fails to bend in response when the entire package receives force and thus bends.Type: ApplicationFiled: February 14, 2001Publication date: October 25, 2001Inventors: Masato Sumikawa, Kazumi Tanaka