Abstract: When a transmission-line driver circuit that transmits a signal to a transmission line is supplied with a power-supply voltage from a power-supply circuit, the value of the power-supply voltage is controlled based upon the amplitude of a signal output from the transmission-line driver circuit. For example, the maximum value of a signal input to the transmission-line driver circuit in time units delimited at fixed time periods is detected, the target value of power-supply voltage supplied to the transmission-line driver circuit is decided based upon the maximum value, and the power-supply circuit is controlled in such a manner that the target value of power-supply voltage and actual value of power-supply voltage will agree.

Abstract: The present invention relates to an analog/digital converter including an analog conversion unit including a plurality of stages having a pipelined configuration and a digital conversion unit. The digital conversion unit has digital-value storage registers, which are each provided for one of the stages. Each of the register is used for storing a digital value completing error correction for each segment, and adapted to output the digital value that corresponds to a segment number. The digital conversion unit also has an error-computation control unit, which controls the stages so that a specific one of the stages, inputs an error computation analog signal. The error-computation control unit then computes an error of the specific stage on the basis of digital-converted data computed from the digital values corresponding to segment numbers received from all the stages following the specific stage.

Abstract: The present invention relates to an analog/digital converter including an analog conversion unit including a plurality of stages having a pipelined configuration and a digital conversion unit. The digital conversion unit has digital-value storage registers, which are each provided for one of the stages. Each of the register is used for storing a digital value completing error correction for each segment, and adapted to output the digital value that corresponds to a segment number. The digital conversion unit also has an error-computation control unit, which controls the stages so that a specific one of the stages inputs an error computation analog signal. The error-computation control unit then computes an error of the specific stage on the basis of digital-converted data computed from the digital values corresponding to segment numbers received from all the stages following the specific stage.

Abstract: An evaluation circuit 16 repeats processing in which an output VD thereof is reset, there is obtained repeatedly given times a difference between sampled output voltages Vo of a replica circuit 11R when respective times t1 and t2 have elapsed after a voltage Vi is step-inputted to the replica circuit 11R, and the differences are successively summed. A comparator circuit 20 compares a difference cumulation voltage VD with a reference voltage VS. A bias adjustment circuit 15 steps up the bias currents of the replica circuit 11R and an adjusted circuit 11 at every this given times if VD>VS, and ceases the adjustment if VD<VS.

Abstract: When a transmission-line driver circuit that transmits a signal to a transmission line is supplied with a power-supply voltage from a power-supply circuit, the value of the power-supply voltage is controlled based upon the amplitude of a signal output from the transmission-line driver circuit. For example, the maximum value of a signal input to the transmission-line driver circuit in time units delimited at fixed time periods is detected, the target value of power-supply voltage supplied to the transmission-line driver circuit is decided based upon the maximum value, and the power-supply circuit is controlled in such a manner that the target value of power-supply voltage and actual value of power-supply voltage will agree.

Abstract: An evaluation circuit 16 repeats processing in which an output VD thereof is reset, there is obtained repeatedly given times a difference between sampled output voltages Vo of a replica circuit 11R when respective times t1 and t2 have elapsed after a voltage Vi is step-inputted to the replica circuit 11R, and the differences are successively summed. A comparator circuit 20 compares a difference cumulation voltage VD with a reference voltage VS. A bias adjustment circuit 15 steps up the bias currents of the replica circuit 11R and an adjusted circuit 11 at every this given times if VD>VS, and ceases the adjustment if VD<VS.

Abstract: A frequency comparator includes a circuit comparing, independently of a phase relationship between first and second clocks, frequencies of the first and second clocks and outputting first and second detection signals when the first clock has frequencies higher and lower than those of the second clock, respectively. The first and second detection signals are output for respective times based on a difference between the frequencies of the first and second clocks.

Abstract: A frequency comparator includes a circuit comparing, independently of a phase relationship between first and second clocks, frequencies of the first and second clocks and outputting first and second detection signals when the first clock has frequencies higher and lower than those of the second clock, respectively. The first and second detection signals are output for respective times based on a difference between the frequencies of the first and second clocks.

Abstract: A transmission-line loss equalizing circuit includes an equalizer, a gain control circuit for controlling the gain of the equalizer based upon the peak value of an equalized output, a slicer for slicing the equalized output and outputting a data pulse, a timing extraction pulse and an equalization control pulse, a DC feedback level detector for detecting a DC component of the equalized output and feeding the DC component back to the equalizer, and an attenuating circuit provided as an initial stage of the equalizer. A plurality of .sqroot.fAGC circuits constructing the equalizer are cascade-connected and constructed by a differential non-inverting amplifier.

Abstract: An evaluation circuit 16 repeats processing in which an output VD thereof is reset, there is obtained repeatedly given times a difference between sampled output voltages Vo of a replica circuit 11R when respective times t1 and t2 have elapsed after a voltage Vi is step-inputted to the replica circuit 11R, and the differences are successively summed. A comparator circuit 20 compares a difference cumulation voltage VD with a reference voltage VS. A bias adjustment circuit 15 steps up the bias currents of the replica circuit 11R and an adjusted circuit 11 at every this given times if VD>VS, and ceases the adjustment if VD<VS.