Abstract: A computer-readable recording medium stores therein an IP model that combines source code of IPs that include an interface representing input/output of data; a register storing the data; a behavior executing processing based on the data; and a state performing wait processing according to time information from the interface and a connection code indicative of a connecting relation between the IPs.

Abstract: A simulation method and apparatus including a restore point setting unit setting restore points in core models for executing threads using parallel processing. The method also includes storing information for reproducing a state the core models at the restore points.

Abstract: A software/hardware (SW/HW) partitioning and evaluating program allows a computer to perform a procedure of compiling a source code in which a mark is added to a portion to be executed by hardware, a procedure of generating an executable program for a simulator of CPU on a system-on-chip (SoC), a procedure of storing in memory an execution result of the executable program, and a procedure of evaluating an SW/HW partition based on the execution result.

Abstract: A high-speed multicore model simulator is realized. A multicore model simulator having a plurality of threads, and a plurality of core models executing the aforesaid plurality of threads is provided. The plurality of core models are a plurality of processor core models, each of which executes one thread, and they are synchronized with each other every predetermined number of execution instructions of each thread.

Abstract: A computer-readable recording medium stores therein an IP model that combines source code of IPs that include an interface representing input/output of data; a register storing the data; a behavior executing processing based on the data; and a state performing wait processing according to time information from the interface and a connection code indicative of a connecting relation between the IPs.

Abstract: It is determined whether an i-th instruction is for a memory access. If the i-th instruction is the memory access, it is determined whether an address to access according to the i-th instruction coincides with an address that has been accessed by a first execution block. If the addresses coincide with each other, it is determined whether a cycle of a second execution block currently executing precedes that of the first execution block. If the cycle of the second execution block precedes that of the first executing block, a memory model is accessed. A necessary number of cycles for execution of a j-th instruction is added to the current number of cycles, and the address, a cycle, data, and a data size at the time of the current access (before re-writing) are written in a delay table.

Abstract: A model managing apparatus manages an intellectual property model formed by using program description to model a function to be realized as hardware. The model managing apparatus includes a data storing unit that stores and manages therein electronic system levels that are components into which the intellectual property model is divided. The components are an application program interface that defines external communications, a register that defines data to be input and output, and a behavior that defines a function or a computation. The data storing unit further stores therein connection data that defines connection relations between the register and the behavior, between behaviors, and between the behavior and the application program interface.

Abstract: Core model processing of a processor model PE1 and a processor model PE2 is serialized. Therefore, processing time for the inter-core-model communication is required between the core model processing of a first processor model and the core model processing of a second processor model. The inter-core-model communication processing is performed such that the inter-core-model communication required for the simulation processing of a multi-processor model is performed in parallel with the core model processing.

Abstract: A method of simulating software by use of a computer includes executing a program inclusive of a plurality of threads by a hardware model implemented as software on a software simulator, utilizing a monitor function of the simulator to collect information about accesses by monitoring accesses made by the plurality of threads with respect to resources provided in the hardware model, utilizing the monitor function to detect, from the collected information, overlapping accesses made to an identical resource area by two or more of the threads, and utilizing the monitor function to generate a message for warning of the overlapping accesses.

Abstract: A simulation method and apparatus including a restore point setting unit setting restore points in core models for executing threads using parallel processing. The method also includes storing information for reproducing a state the core models at the restore points.

Abstract: A computer is made to execute the procedures of separating a hardware side from a software side within a reference source, and generating a merge model comprising a firmware interface for the software side to call the hardware side and comprising a hardware interface enabling an access to a mathematical function or a variable on the hardware side in response to a call from the firmware interface; and generating a system-on-chip (SoC) model comprising a CPU model for implementing a firmware interface with the software side, a hardware model for implementing the hardware side and a hardware interface connecting the CPU model to the hardware model.

Abstract: A SW/HW partitioning and evaluating program allows a computer to perform a procedure of compiling a source code in which a mark is added to a portion to be executed by hardware, a procedure of generating an executable program for a simulator of CPU on a SoC, a procedure of storing in memory an execution result of the executable program, and a procedure of evaluating an SW/HW partition based on the execution result.

Abstract: It is determined whether an i-th instruction is for a memory access. If the i-th instruction is the memory access, it is determined whether an address to access according to the i-th instruction coincides with an address that has been accessed by a first execution block. If the addresses coincide with each other, it is determined whether a cycle of a second execution block currently executing precedes that of the first execution block. If the cycle of the second execution block precedes that of the first executing block, a memory model is accessed. A necessary number of cycles for execution of a j-th instruction is added to the current number of cycles, and the address, a cycle, data, and a data size at the time of the current access (before re-writing) are written in a delay table.

Abstract: Core model processing of a processor model PE1 and a processor model PE2 is serialized. Therefore, processing time for the inter-core-model communication is required between the core model processing of a first processor model and the core model processing of a second processor model. The inter-core-model communication processing is performed such that the inter-core-model communication required for the simulation processing of a multi-processor model is performed in parallel with the core model processing.

Abstract: A system simulation method preventing the simulation speed from lowering. An initialization section allocates an area corresponding to a certain area on a memory model to be accessed by a user hardware model, as a user hardware memory, on a computer memory. Memory access from the user hardware model is always made to the user hardware memory. An access control section enables memory access from a processor core model to the user hardware memory and controls the memory access so that no conflict occurs with the access from the user hardware model.

Abstract: A high-speed multicore model simulator is realized. A multicore model simulator having a plurality of threads, and a plurality of core models executing the aforesaid plurality of threads is provided. The plurality of core models are a plurality of processor core models, each of which executes one thread, and they are synchronized with each other every predetermined number of execution instructions of each thread.

Abstract: A zero determination signal generating circuit which generates a zero determination signal for determining whether or not the output data of a shifter is zero is provided. With the zero determination signal generating circuit of the present invention, high-speed zero determination can be achieved. More specifically, in a case where the shifter functions as a left shifter, as a shifting operation of a left shifter unit (including a plurality of left shifters) is performed, predetermined bits in the outputs of left shifters having a shift amount of 0 are subjected to an OR operation or buffered so as to generate a zero determination signal. In a case where the shifter functions as a right shifter, as a shifting operation of a right shifter unit (including a plurality of right shifters) is performed, predetermined bits in the outputs of right shifters having a shift amount of 0 are subjected to an OR operation or buffered so as to generate a zero determination signal.

Abstract: A CMOS IC device operating at a frequency of 300 MHz or higher includes a power supply wiring for interconnecting one of circuit elements and a power supply pad, and a phase-shifting split wiring connected to the power supply wiring and not directly connected to any circuit elements, only for producing a noise phase difference between noises on the power supply wiring and the phase-shifting split wiring. A signal entering from the phase-shifting split wiring has a phase different from the phase of a signal transmitted on the power supply wiring to thereby reduce spike noises.