Patents by Inventor Masatomi Okanishi
Masatomi Okanishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9472563Abstract: A semiconductor device includes bit lines (12) that are provided in a semiconductor substrate (10) an ONO film (14) that is provided on the semiconductor substrate; word lines that are provided on the ONO film (14) and extend in a width direction of the bit lines (12); and a dummy layer (44) that extends in the width direction of the bit lines (12) and is provided in a bit-line contact region (40) having contact holes formed to connect the bit lines (12) with wiring layers (34). In accordance with the present invention, the proximity effect at the time of word line formation can be restrained, and the variation in the widths of the word lines can be made smaller, or current leakage between the bit lines and the semiconductor substrate can be restrained.Type: GrantFiled: December 12, 2011Date of Patent: October 18, 2016Assignee: Cypress Semiconductor CorporationInventor: Masatomi Okanishi
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Publication number: 20120315750Abstract: A semiconductor device includes bit lines (12) that are provided in a semiconductor substrate (10) an ONO film (14) that is provided on the semiconductor substrate; word lines that are provided on the ONO film (14) and extend in a width direction of the bit lines (12); and a dummy layer (44) that extends in the width direction of the bit lines (12) and is provided in a bit-line contact region (40) having contact holes formed to connect the bit lines (12) with wiring layers (34). In accordance with the present invention, the proximity effect at the time of word line formation can be restrained, and the variation in the widths of the word lines can be made smaller, or current leakage between the bit lines and the semiconductor substrate can be restrained.Type: ApplicationFiled: December 12, 2011Publication date: December 13, 2012Inventor: Masatomi Okanishi
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Patent number: 8183622Abstract: A semiconductor device includes bit lines (12) that are provided in a semiconductor substrate (10) an ONO film (14) that is provided on the semiconductor substrate; word lines that are provided on the ONO film (14) and extend in a width direction of the bit lines (12); and a dummy layer (44) that extends in the width direction of the bit lines (12) and is provided in a bit-line contact region (40) having contact holes formed to connect the bit lines (12) with wiring layers (34). In accordance with the present invention, the proximity effect at the time of word line formation can be restrained, and the variation in the widths of the word lines can be made smaller, or current leakage between the bit lines and the semiconductor substrate can be restrained.Type: GrantFiled: July 27, 2006Date of Patent: May 22, 2012Assignee: Spansion LLCInventor: Masatomi Okanishi
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Publication number: 20120083086Abstract: There is provided a semiconductor device including a semiconductor substrate (10), a high concentration diffusion region (22) formed within the semiconductor substrate (10), a first low concentration region (24) that has a lower impurity concentration than the high concentration diffusion region (22) and is provided under the high concentration diffusion region (22), and a bit line (30) that includes the high concentration diffusion region (22) and the first low concentration diffusion region (24) and serves as a source region and a drain region, and a manufacturing method therefor. Reduction of source-drain breakdown voltage of the transistor is suppressed, and a low-resistance bit line can be formed. Thus, a semiconductor device that can miniaturize memory cells and a manufacturing method therefor can be provided.Type: ApplicationFiled: December 12, 2011Publication date: April 5, 2012Inventor: Masatomi OKANISHI
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Patent number: 8097518Abstract: There is provided a semiconductor device including a semiconductor substrate (10), a high concentration diffusion region (22) formed within the semiconductor substrate (10), a first low concentration diffusion region (24) that has a lower impurity concentration than the high concentration diffusion region (22) and is provided under the high concentration diffusion region (22), and a bit line(30) that includes the high concentration diffusion region (22) and the first low concentration diffusion region (24) and serves as a source region and a drain region, and a manufacturing method therefor. Reduction of source-drain breakdown voltage of the transistor is suppressed, and a low-resistance bit line can be formed. Thus, a semiconductor device that can miniaturize memory cells and a manufacturing method therefor can be provided.Type: GrantFiled: October 6, 2010Date of Patent: January 17, 2012Assignee: Spansion LLCInventor: Masatomi Okanishi
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Patent number: 7915661Abstract: The present invention provides semiconductor device and a fabrication method therefor. The semiconductor device includes trenches (11) formed in a semiconductor substrate (10), first ONO films (18) provided on both side surfaces of the trenches, and first word lines (22) provided on side surfaces of the first ONO films (18) and running in a length direction of the trenches (11). According to the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, in which higher memory capacity can be achieved.Type: GrantFiled: August 18, 2009Date of Patent: March 29, 2011Assignee: Spansion LLCInventors: Masaya Hosaka, Masatomi Okanishi
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Publication number: 20110020996Abstract: There is provided a semiconductor device including a semiconductor substrate (10), a high concentration diffusion region (22) formed within the semiconductor substrate (10), a first low concentration diffusion region (24) that has a lower impurity concentration than the high concentration diffusion region (22) and is provided under the high concentration diffusion region (22), and a bit line(30) that includes the high concentration diffusion region (22) and the first low concentration diffusion region (24) and serves as a source region and a drain region, and a manufacturing method therefor. Reduction of source-drain breakdown voltage of the transistor is suppressed, and a low-resistance bit line can be formed. Thus, a semiconductor device that can miniaturize memory cells and a manufacturing method therefor can be provided.Type: ApplicationFiled: October 6, 2010Publication date: January 27, 2011Inventor: Masatomi OKANISHI
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Patent number: 7847340Abstract: The present invention provides a semiconductor device and a method of manufacturing the semiconductor device, the semiconductor device including: ONO films that are formed on a semiconductor substrate and include trapping layers; word lines that are formed on the ONO films; and silicon oxide layers that are formed at portions on the semiconductor substrate, the portions being located between the word lines, the silicon oxide layers being located between the trapping layers.Type: GrantFiled: December 21, 2007Date of Patent: December 7, 2010Assignee: Spansion LLCInventors: Kenichi Fujii, Masatomi Okanishi
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Patent number: 7825457Abstract: There is provided a semiconductor device including a semiconductor substrate (10), a high concentration diffusion region (22) formed within the semiconductor substrate (10), a first low concentration diffusion region (24) that has a lower impurity concentration than the high concentration diffusion region (22) and is provided under the high concentration diffusion region (22), and a bit line (30) that includes the high concentration diffusion region (22) and the first low concentration diffusion region (24) and serves as a source region and a drain region, and a manufacturing method therefor. Reduction of source-drain breakdown voltage of the transistor is suppressed, and a low-resistance bit line can be formed. Thus, a semiconductor device that can miniaturize memory cells and a manufacturing method therefor can be provided.Type: GrantFiled: April 27, 2006Date of Patent: November 2, 2010Assignee: Spansion LLCInventor: Masatomi Okanishi
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Patent number: 7825448Abstract: A semiconductor device and a method for manufacturing thereof are provided. The semiconductor device includes two epitaxial semiconductor layers formed on a semiconductor substrate, bit lines formed on upper portions of the two epitaxial semiconductor layers, and a charge storage layer formed on the semiconductor substrate between the two epitaxial semiconductor layers.Type: GrantFiled: August 15, 2008Date of Patent: November 2, 2010Assignee: Spansion LLCInventors: Masatomi Okanishi, Yoshihiro Mikasa, Hiroshi Murai
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Publication number: 20100001333Abstract: The present invention provides semiconductor device and a fabrication method therefor. The semiconductor device includes trenches (11) formed in a semiconductor substrate (10), first ONO films (18) provided on both side surfaces of the trenches, and first word lines (22) provided on side surfaces of the first ONO films (18) and running in a length direction of the trenches (11). According to the present invention, it is possible to provide a semiconductor deice and a fabrication method therefor, in which higher memory capacity can be achieved.Type: ApplicationFiled: August 18, 2009Publication date: January 7, 2010Inventors: Masaya Hosaka, Masatomi Okanishi
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Patent number: 7589371Abstract: The present invention provides semiconductor device and a fabrication method therefor. The semiconductor device includes trenches (11) formed in a semiconductor substrate (10), first ONO films (18) provided on both side surfaces of the trenches, and first word lines (22) provided on side surfaces of the first ONO films (18) and running in a length direction of the trenches (11). According to the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, in which higher memory capacity can be achieved.Type: GrantFiled: August 30, 2006Date of Patent: September 15, 2009Assignee: Spansion LLCInventors: Masaya Hosaka, Masatomi Okanishi
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Publication number: 20090200599Abstract: A semiconductor device and a method for manufacturing thereof are provided. The semiconductor device includes two epitaxial semiconductor layers formed on a semiconductor substrate, bit lines formed on upper portions of the two epitaxial semiconductor layers, and a charge storage layer formed on the semiconductor substrate between the two epitaxial semiconductor layers.Type: ApplicationFiled: August 15, 2008Publication date: August 13, 2009Inventors: Masatomi OKANISHI, Yoshihiro MIKASA, Hiroshi Murai
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Publication number: 20080191321Abstract: The present invention provides a semiconductor device and a method of manufacturing the semiconductor device, the semiconductor device including: ONO films that are formed on a semiconductor substrate and include trapping layers; word lines that are formed on the ONO films; and silicon oxide layers that are formed at portions on the semiconductor substrate, the portions being located between the word lines, the silicon oxide layers being located between the trapping layers.Type: ApplicationFiled: December 21, 2007Publication date: August 14, 2008Applicant: SPANSION LLCInventors: Kenichi FUJII, Masatomi OKANISHI
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Patent number: 7387936Abstract: A semiconductor device includes a substrate having a pair of first diffused regions, and a gate including an oxide film provided on the substrate, and a charge storage layer provided on the oxide film, the charge storage layer being an electrical insulator capable of storing charges in bit areas. The oxide film has first portions related to the bit areas and a second portion that is located between the bit areas and is thicker than the first potions. The first portions serve as tunneling oxide portions, while the second portion allows reduced tunneling.Type: GrantFiled: October 23, 2007Date of Patent: June 17, 2008Assignee: Spansion LLCInventor: Masatomi Okanishi
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Publication number: 20080064181Abstract: A semiconductor device includes a substrate having a pair of first diffused regions, and a gate including an oxide film provided on the substrate, and a charge storage layer provided on the oxide film, the charge storage layer being an electrical insulator capable of storing charges in bit areas. The oxide film has first portions related to the bit areas and a second portion that is located between the bit areas and is thicker than the first potions. The first portions serve as tunneling oxide portions, while the second portion allows reduced tunneling.Type: ApplicationFiled: October 23, 2007Publication date: March 13, 2008Inventor: Masatomi Okanishi
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Patent number: 7309893Abstract: A semiconductor device includes a substrate having a pair of first diffused regions, and a gate including an oxide film provided on the substrate, and a charge storage layer provided on the oxide film, the charge storage layer being an electrical insulator capable of storing charges in bit areas. The oxide film has first portions related to the bit areas and a second portion that is located between the bit areas and is thicker than the first potions. The first portions serve as tunneling oxide portions, while the second portion allows reduced tunneling.Type: GrantFiled: June 14, 2005Date of Patent: December 18, 2007Assignee: Spansion LLCInventor: Masatomi Okanishi
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Publication number: 20070105308Abstract: The present invention provides semiconductor device and a fabrication method therefor. The semiconductor device includes trenches (11) formed in a semiconductor substrate (10), first ONO films (18) provided on both side surfaces of the trenches, and first word lines (22) provided on side surfaces of the first ONO films (18) and running in a length direction of the trenches (11). According to the present invention, it is possible to provide a semiconductor deice and a fabrication method therefor, in which higher memory capacity can be achieved.Type: ApplicationFiled: August 30, 2006Publication date: May 10, 2007Inventors: Masaya Hosaka, Masatomi Okanishi
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Publication number: 20070052017Abstract: There is provided a semiconductor device including a semiconductor substrate (10), a high concentration diffusion region (22) formed within the semiconductor substrate (10), a first low concentration diffusion region (24) that has a lower impurity concentration than the high concentration diffusion region (22) and is provided under the high concentration diffusion region (22), and a bit line(30) that includes the high concentration diffusion region (22) and the first low concentration diffusion region (24) and serves as a source region and a drain region, and a manufacturing method therefor. Reduction of source-drain breakdown voltage of the transistor is suppressed, and a low-resistance bit line can be formed. Thus, a semiconductor device that can miniaturize memory cells and a manufacturing method therefor can be provided.Type: ApplicationFiled: April 27, 2006Publication date: March 8, 2007Inventor: Masatomi Okanishi
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Publication number: 20070026604Abstract: A semiconductor device includes bit lines (12) that are provided in a semiconductor substrate (10) an ONO film (14) that is provided on the semiconductor substrate; word lines that are provided on the ONO film (14) and extend in a width direction of the bit lines (12); and a dummy layer (44) that extends in the width direction of the bit lines (12) and is provided in a bit-line contact region (40) having contact holes formed to connect the bit lines (12) with wiring layers (34). In accordance with the present invention, the proximity effect at the time of word line formation can be restrained, and the variation in the widths of the word lines can be made smaller, or current leakage between the bit lines and the semiconductor substrate can be restrained.Type: ApplicationFiled: July 27, 2006Publication date: February 1, 2007Inventor: Masatomi Okanishi