Patents by Inventor Masatoshi Aketa
Masatoshi Aketa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230377973Abstract: A method for manufacturing a semiconductor device includes a step of preparing a semiconductor wafer source which includes a first main surface on one side, a second main surface on the other side and a side wall connecting the first main surface and the second main surface, an element forming step of setting a plurality of element forming regions on the first main surface of the semiconductor wafer source, and forming a semiconductor element at each of the plurality of element forming regions, and a wafer source separating step of cutting the semiconductor wafer source from a thickness direction intermediate portion along a horizontal direction parallel to the first main surface, and separating the semiconductor wafer source into an element formation wafer and an element non-formation wafer after the element forming step.Type: ApplicationFiled: July 18, 2023Publication date: November 23, 2023Applicant: ROHM CO., LTD.Inventors: Masatoshi AKETA, Kazunori FUJI
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Publication number: 20230361210Abstract: A semiconductor device includes a semiconductor layer having a first surface and a second surface, a unit cell including a diode region of a first conductivity type formed in a surface layer portion of the first surface of the semiconductor layer, a well region of a second conductivity type formed in the surface layer portion of the first surface of the semiconductor layer along a peripheral edge of the diode region, and a first conductivity type region formed in a surface layer portion of the well region, a gate electrode layer facing the well region and the first conductivity type region through a gate insulating layer and a first surface electrode covering the diode region and the first conductivity type region on the first surface of the semiconductor layer, and forming a Schottky junction with the diode region and an ohmic junction with the first conductivity type region.Type: ApplicationFiled: July 17, 2023Publication date: November 9, 2023Applicant: ROHM CO., LTD.Inventors: Takui SAKAGUCHI, Masatoshi AKETA, Yuki NAKANO
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Patent number: 11749749Abstract: A semiconductor device includes a semiconductor layer having a first main surface on one side and a second main surface on the other side, a unit cell including a diode region of a first conductivity type formed in a surface layer portion of the first main surface of the semiconductor layer, a well region of a second conductivity type formed in the surface layer portion of the first main surface of the semiconductor layer along a peripheral edge of the diode region, and a first conductivity type region formed in a surface layer portion of the well region, a gate electrode layer facing the well region and the first conductivity type region through a gate insulating layer and a first main surface electrode covering the diode region and the first conductivity type region on the first main surface of the semiconductor layer, and forming a Schottky junction with the diode region and an ohmic junction with the first conductivity type region.Type: GrantFiled: July 9, 2021Date of Patent: September 5, 2023Assignee: ROHM CO., LTD.Inventors: Takui Sakaguchi, Masatoshi Aketa, Yuki Nakano
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Patent number: 11742243Abstract: A method for manufacturing a semiconductor device includes a step of preparing a semiconductor wafer source which includes a first main surface on one side, a second main surface on the other side and a side wall connecting the first main surface and the second main surface, an element forming step of setting a plurality of element forming regions on the first main surface of the semiconductor wafer source, and forming a semiconductor element at each of the plurality of element forming regions, and a wafer source separating step of cutting the semiconductor wafer source from a thickness direction intermediate portion along a horizontal direction parallel to the first main surface, and separating the semiconductor wafer source into an element formation wafer and an element non-formation wafer after the element forming step.Type: GrantFiled: January 27, 2022Date of Patent: August 29, 2023Assignee: ROHM CO., LTD.Inventors: Masatoshi Aketa, Kazunori Fuji
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Publication number: 20230253510Abstract: The semiconductor device of the present invention includes a first conductivity type semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode formed to come into contact with a surface of the semiconductor layer, and has a threshold voltage Vth of 0.3 V to 0.7 V and a leakage current Jr of 1×10?9 A/cm2 to 1×10?4 A/cm2 in a rated voltage VR.Type: ApplicationFiled: April 17, 2023Publication date: August 10, 2023Inventors: Masatoshi AKETA, Yuta YOKOTSUJI
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Publication number: 20230187486Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a first main surface at one side and a second main surface at another side, a trench gate structure including a gate trench formed in the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer, a trench source structure including a source trench formed deeper than the gate trench and across an interval from the gate trench in the first main surface of the semiconductor layer, a source electrode embedded in the source trench, and a deep well region of a second conductivity type formed in a region of the semiconductor layer along the source trench, a ratio of a depth of the trench source structure with respect to a depth of the trench gate structure being not less than 1.5 and not more than 4.Type: ApplicationFiled: February 6, 2023Publication date: June 15, 2023Inventors: Minoru NAKAGAWA, Yuki NAKANO, Masatoshi AKETA, Masaya UENO, Seigo MORI, Kenji YAMAMOTO
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Patent number: 11664465Abstract: The semiconductor device of the present invention includes a first conductivity type semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode formed to come into contact with a surface of the semiconductor layer, and has a threshold voltage Vth of 0.3 V to 0.7 V and a leakage current Jr of 1×10?9 A/cm2 to 1×10?4 A/cm2 in a rated voltage VR.Type: GrantFiled: May 9, 2022Date of Patent: May 30, 2023Assignee: ROHM CO., LTD.Inventors: Masatoshi Aketa, Yuta Yokotsuji
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Patent number: 11605707Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a first main surface at one side and a second main surface at another side, a trench gate structure including a gate trench formed in the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer, a trench source structure including a source trench formed deeper than the gate trench and across an interval from the gate trench in the first main surface of the semiconductor layer, a source electrode embedded in the source trench, and a deep well region of a second conductivity type formed in a region of the semiconductor layer along the source trench, a ratio of a depth of the trench source structure with respect to a depth of the trench gate structure being not less than 1.5 and not more than 4.Type: GrantFiled: June 16, 2021Date of Patent: March 14, 2023Assignee: ROHM CO., LTD.Inventors: Minoru Nakagawa, Yuki Nakano, Masatoshi Aketa, Masaya Ueno, Seigo Mori, Kenji Yamamoto
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Publication number: 20230019556Abstract: A semiconductor device includes a SiC semiconductor layer that has a carbon density of 1.0×1022 cm-3 or more, a SiO2 layer that is formed on the SiC semiconductor layer and that has a connection surface contiguous to the SiC semiconductor layer and a non-connection surface positioned on a side opposite to the connection surface, a carbon-density-decreasing region that is formed at a surface layer portion of the connection surface of the SiO2 layer and in which a carbon density gradually decreases toward the non-connection surface of the SiO2 layer, and a low carbon density region that is formed at a surface layer portion of the non-connection surface of the SiO2 layer and that has a carbon density of 1.0×1019 cm-3 or less.Type: ApplicationFiled: September 28, 2022Publication date: January 19, 2023Inventors: Tsunenobu KIMOTO, Takuma KOBAYASHI, Yuki NAKANO, Masatoshi AKETA
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Patent number: 11502172Abstract: A semiconductor device includes a SiC semiconductor layer that has a carbon density of 1.0×1022 cm?3 or more, a SiO2 layer that is formed on the SiC semiconductor layer and that has a connection surface contiguous to the SiC semiconductor layer and a non-connection surface positioned on a side opposite to the connection surface, a carbon-density-decreasing region that is formed at a surface layer portion of the connection surface of the SiO2 layer and in which a carbon density gradually decreases toward the non-connection surface of the SiO2 layer, and a low carbon density region that is formed at a surface layer portion of the non-connection surface of the SiO2 layer and that has a carbon density of 1.0×1019 cm?3 or less.Type: GrantFiled: January 10, 2019Date of Patent: November 15, 2022Assignee: ROHM CO., LTD.Inventors: Tsunenobu Kimoto, Takuma Kobayashi, Yuki Nakano, Masatoshi Aketa
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Publication number: 20220271174Abstract: The semiconductor device of the present invention includes a first conductivity type semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode formed to come into contact with a surface of the semiconductor layer, and has a threshold voltage Vth of 0.3 V to 0.7 V and a leakage current Jr of 1×10?9 A/cm2 to 1×10?4 A/cm2 in a rated voltage VR.Type: ApplicationFiled: May 9, 2022Publication date: August 25, 2022Inventors: Masatoshi AKETA, Yuta YOKOTSUJI
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Patent number: 11355651Abstract: The semiconductor device of the present invention includes a first conductivity type semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode formed to come into contact with a surface of the semiconductor layer, and has a threshold voltage Vth of 0.3 V to 0.7 V and a leakage current Jr of 1×10?9 A/cm2 to 1×10?4 A/cm2 in a rated voltage VR.Type: GrantFiled: January 14, 2021Date of Patent: June 7, 2022Assignee: ROHM CO., LTD.Inventors: Masatoshi Aketa, Yuta Yokotsuji
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Publication number: 20220148922Abstract: A method for manufacturing a semiconductor device includes a step of preparing a semiconductor wafer source which includes a first main surface on one side, a second main surface on the other side and a side wall connecting the first main surface and the second main surface, an element forming step of setting a plurality of element forming regions on the first main surface of the semiconductor wafer source, and forming a semiconductor element at each of the plurality of element forming regions, and a wafer source separating step of cutting the semiconductor wafer source from a thickness direction intermediate portion along a horizontal direction parallel to the first main surface, and separating the semiconductor wafer source into an element formation wafer and an element non-formation wafer after the element forming step.Type: ApplicationFiled: January 27, 2022Publication date: May 12, 2022Inventors: Masatoshi AKETA, Kazunori FUJI
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Publication number: 20220115342Abstract: An electronic component includes a substrate having a first main surface on one side and a second main surface on the other side, a chip having a first chip main surface on one side and a second chip main surface on the other side, and a plurality of electrodes formed on the first chip main surface and/or the second chip main surface, the chip being arranged on the first main surface of the substrate, a sealing insulation layer that seals the chip on the first main surface of the substrate such that the second main surface of the substrate is exposed, the sealing insulation layer having a sealing main surface that opposes the first main surface of the substrate, and a plurality of external terminals formed to penetrate through the sealing insulation layer so as to be exposed from the sealing main surface of the sealing insulation layer, the external terminals being respectively electrically connected to the plurality of electrodes of the chip.Type: ApplicationFiled: December 17, 2021Publication date: April 14, 2022Inventor: Masatoshi AKETA
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Patent number: 11264280Abstract: A method for manufacturing a semiconductor device includes a step of preparing a semiconductor wafer source which includes a first main surface on one side, a second main surface on the other side and a side wall connecting the first main surface and the second main surface, an element forming step of setting a plurality of element forming regions on the first main surface of the semiconductor wafer source, and forming a semiconductor element at each of the plurality of element forming regions, and a wafer source separating step of cutting the semiconductor wafer source from a thickness direction intermediate portion along a horizontal direction parallel to the first main surface, and separating the semiconductor wafer source into an element formation wafer and an element non-formation wafer after the element forming step.Type: GrantFiled: June 19, 2018Date of Patent: March 1, 2022Assignee: ROHM CO., LTD.Inventors: Masatoshi Aketa, Kazunori Fuji
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Patent number: 11239189Abstract: An electronic component includes a substrate having a first main surface on one side and a second main surface on the other side, a chip having a first chip main surface on one side and a second chip main surface on the other side, and a plurality of electrodes formed on the first chip main surface and/or the second chip main surface, the chip being arranged on the first main surface of the substrate, a sealing insulation layer that seals the chip on the first main surface of the substrate such that the second main surface of the substrate is exposed, the sealing insulation layer having a sealing main surface that opposes the first main surface of the substrate, and a plurality of external terminals formed to penetrate through the sealing insulation layer so as to be exposed from the sealing main surface of the sealing insulation layer, the external terminals being respectively electrically connected to the plurality of electrodes of the chip.Type: GrantFiled: April 20, 2018Date of Patent: February 1, 2022Assignee: ROHM CO., LTD.Inventor: Masatoshi Aketa
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Publication number: 20210336049Abstract: A semiconductor device includes a semiconductor layer having a first main surface on one side and a second main surface on the other side, a unit cell including a diode region of a first conductivity type formed in a surface layer portion of the first main surface of the semiconductor layer, a well region of a second conductivity type formed in the surface layer portion of the first main surface of the semiconductor layer along a peripheral edge of the diode region, and a first conductivity type region formed in a surface layer portion of the well region, a gate electrode layer facing the well region and the first conductivity type region through a gate insulating layer and a first main surface electrode covering the diode region and the first conductivity type region on the first main surface of the semiconductor layer, and forming a Schottky junction with the diode region and an ohmic junction with the first conductivity type region.Type: ApplicationFiled: July 9, 2021Publication date: October 28, 2021Inventors: Takui SAKAGUCHI, Masatoshi AKETA, Yuki NAKANO
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Publication number: 20210305363Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a first main surface at one side and a second main surface at another side, a trench gate structure including a gate trench formed in the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer, a trench source structure including a source trench formed deeper than the gate trench and across an interval from the gate trench in the first main surface of the semiconductor layer, a source electrode embedded in the source trench, and a deep well region of a second conductivity type formed in a region of the semiconductor layer along the source trench, a ratio of a depth of the trench source structure with respect to a depth of the trench gate structure being not less than 1.5 and not more than 4.Type: ApplicationFiled: June 16, 2021Publication date: September 30, 2021Inventors: Minoru NAKAGAWA, Yuki NAKANO, Masatoshi AKETA, Masaya UENO, Seigo MORI, Kenji YAMAMOTO
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Publication number: 20210305369Abstract: An SiC semiconductor device includes an SiC semiconductor layer having a first main surface and a second main surface, a gate electrode embedded in a trench with a gate insulating layer, a source region of a first conductivity type formed in a side of the trench in a surface layer portion of the first main surface, a body region of a second conductivity type formed in a region at the second main surface side with respect to the source region in the surface layer portion of the first main surface, a drift region of the first conductivity type formed in a region at the second main surface side in the SiC semiconductor layer, and a contact region of the second conductivity type having an impurity concentration of not more than 1.0×1020 cm?3 and formed in the surface layer portion of the first main surface.Type: ApplicationFiled: August 5, 2019Publication date: September 30, 2021Inventors: Yuki NAKANO, Masatoshi AKETA, Takui SAKAGUCHI, Yuichiro NANEN
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Patent number: 11088272Abstract: A semiconductor device includes a semiconductor layer having a first main surface on one side and a second main surface on the other side, a unit cell including a diode region of a first conductivity type formed in a surface layer portion of the first main surface of the semiconductor layer, a well region of a second conductivity type formed in the surface layer portion of the first main surface of the semiconductor layer along a peripheral edge of the diode region, and a first conductivity type region formed in a surface layer portion of the well region, a gate electrode layer facing the well region and the first conductivity type region through a gate insulating layer and a first main surface electrode covering the diode region and the first conductivity type region on the first main surface of the semiconductor layer, and forming a Schottky junction with the diode region and an ohmic junction with the first conductivity type region.Type: GrantFiled: January 25, 2018Date of Patent: August 10, 2021Assignee: ROHM CO., LTD.Inventors: Takui Sakaguchi, Masatoshi Aketa, Yuki Nakano