Patents by Inventor Masatoshi Nakasu

Masatoshi Nakasu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050286194
    Abstract: The object of the invention is to protect a power MOS transistor using a transistor having trench structure from overcurrent and to enhance the reliability. To achieve the object, a power MOS transistor, a transistor for detecting current for detecting the current of the power MOS transistor and generating a detection signal supplied to an external control circuit and devices configuring a protection circuit for detecting the current of the power MOS transistor and inhibiting current by forcedly dropping the gate voltage of the power MOS transistor when current equal to or exceeding a predetermined value flows are provided in the same semiconductor chip.
    Type: Application
    Filed: April 22, 2005
    Publication date: December 29, 2005
    Inventors: Atsushi Fujiki, Masatoshi Nakasu
  • Patent number: 6496049
    Abstract: This semiconductor integrated circuit is constituted by any one of a p-channel MOS transistor and an n-channel MOS transistor, and is connected between the control terminal and the common terminal so as to produce predetermined voltage. The comparing circuit is operated in response to a control voltage applied between the control terminal and the common terminal so as to compare the predetermined reference voltage with the current-detected voltage which is obtained from the current detecting circuit. The gate controlling MOS transistor controls a gate voltage of the power MOS transistor based upon the comparison output of the comparing circuit. Then, all of these structural members are formed on the same semiconductor substrate.
    Type: Grant
    Filed: July 19, 2001
    Date of Patent: December 17, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Nobuo Tsukagoshi, Masatoshi Nakasu, Atsushi Fujiki, Kazuaki Ohsawa
  • Publication number: 20020017941
    Abstract: This semiconductor integrated circuit is constituted by any one of a p-channel MOS transistor and an n-channel MOS transistors and is connected between the control terminal and the common terminal so as to produce predetermined voltage. The comparing circuit is operated in response to a control voltage applied between the control terminal and the common terminal so as to compare the predetermined reference voltage with the current-detected voltage which is obtained from the current detecting circuit. The gate controlling MOS transistor controls a gate voltage of the power MOS transistor based upon the comparison output of the comparing circuit. Then, all of these structural members are formed on the same semiconductor substrate.
    Type: Application
    Filed: July 19, 2001
    Publication date: February 14, 2002
    Inventors: Nobuo Tsukagoshi, Masatoshi Nakasu, Atsushi Fujiki, Kazuaki Ohsawa
  • Patent number: 5502338
    Abstract: A power transistor device is provided which has a function of clamping the collector voltage to a stable level for a wide range of temperature variations. In the power transistor device, a plurality of pn junctions are formed to fabricate Zener diodes in the polycrystalline silicon film in the form of rings. The ring configuration of the Zener diodes eliminates an end at the pn junction and prevents the junction surface from being exposed, making it possible to use as a stable Zener voltage the dielectric strength characteristic of the pn junction having a very small temperature coefficient.
    Type: Grant
    Filed: November 18, 1994
    Date of Patent: March 26, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Minoru Suda, Masatoshi Nakasu, Tetsuo Iijima
  • Patent number: 5397914
    Abstract: In a transistor where collector is connected to an inductive load and switching current flows, a Zener diode comprising structure of plural pn-junctions constituted in series form to a polysilicon is provided between collector and base. Further MOSFET is switch-controlled by control voltage formed based on Zener current flowing through the Zener diode, and current path in parallel form to the Zener diode is constituted. Since temperature characteristic coefficient of a Zener diode formed in a polysilicon film is very small, the reverse voltage generated in the inductive load can be set to stable voltage in spite of the temperature variation. Further the MOSFET is provided in parallel form, thereby relatively large ON-resistance value of the Zener diode can be decreased.
    Type: Grant
    Filed: April 27, 1993
    Date of Patent: March 14, 1995
    Assignee: Hitachi Ltd.
    Inventors: Minoru Suda, Masatoshi Nakasu, Tetsuo Iijima