Abstract: A CPU system having a built-in cache memory system in which a write-only port for coherence control from the common system side and an access port from the CPU side are isolated through a multi-port configuration of the cache memory system inside CPU. A common memory on the common side too, uses a 2-port system structure with the CPU system in the form of a broadcast type connection form.

Abstract: A charged particle beam scanning inspecting apparatus for irradiating a charged particle beam, fetching information of a subject to be inspected at a predetermined beam scanning position and performing an inspection by processing the information. The apparatus is a measurer which measures a scanning position of the beam and an inspection position on said inspection subject to calculate beam target coordinates corrected for an apparatus error, an error correction constant and a deflected distortion correction constant, and a deflection controller for scanning the beam. The deflection controller includes a deflection position operating circuit for performing an operation of the inspection position in a deflection coordinate system, a deflected distortion operating circuit. The deflection position operating circuit and deflected distortion operating circuit are constructed in a pipe line fashion.

Abstract: In order that the deflection scanning position can be corrected at a time point within a period for fetching information from a subject to be inspected and improvements in accuracy of chip comparison inspection and an inspection near the wafer outer periphery where distortion is large can be assured by correcting the inspection position and biased distortion at a high speed with high accuracy, a digital deflection control scheme is employed in which the deflection scanning signal and correction are all calculated digitally in a deflection controller for deflecting and controlling a charged particle beam irradiated onto a subject to be inspected and the digital value is sequentially converted into an analog value by a time-series train of digital control signal to form a deflection scanning waveform.

Abstract: In order that the deflection scanning position can be corrected at a time point within a period for fetching information from a subject to be inspected and improvements in accuracy of chip comparison inspection and an inspection near the wafer outer periphery where distortion is large can be assured by correcting the inspection position and biased distortion at a high speed with high accuracy, a digital deflection control scheme is employed in which the deflection scanning signal and correction are all calculated digitally in a deflection controller for deflecting and controlling a charged particle beam irradiated onto a subject to be inspected and the digital value is sequentially converted into an analog value by a time-series train of digital control signal to form a deflection scanning waveform.

Abstract: The present invention aims to prevent degradation in performance due to a change in image quality and deflection distortions or the like in the vicinity of both ends of a scan area and detect a defect in a sample such as a semiconductor wafer or the like with high accuracy when the defect is inspected by use of an electron beam image, and allow a monitor to confirm an image area to be checked. The present invention is provided with means for comparing and checking defects in the sample, based on an image signal in which the neighborhoods of both ends of horizontal and vertical scan areas are respectively deleted under control of a blanking signal and a vertical synchronizing signal.

Abstract: The present invention aims to prevent degradation in performance due to a change in image quality and deflection distortions or the like in the vicinity of both ends of a scan area and detect a defect in a sample such as a semiconductor wafer or the like with high accuracy when the defect is inspected by use of an electron beam image, and allow a monitor to confirm an image area to be checked. The present invention is provided with means for comparing and checking defects in the sample, based on an image signal in which the neighborhoods of both ends of horizontal and vertical scan areas are respectively deleted under control of a blanking signal and a vertical synchronizing signal.

Abstract: A process of contacting sides of a plurality of chips having semiconductor elements formed in a substrate surface, directly to each other on the same {111} crystal plane.

Abstract: A CPU system having a built-in cache memory system in which a write-only port for coherence control from the common system side and an access port from the CPU side are isolated through a multi-port configuration of the cache memory system inside CPU. A common memory on the common side too, uses a 2-port system structure with the CPU system in the form of a broadcast type connection form.

Abstract: A parallel processing system in which access contention of a read cycle from a processing unit side to a local shared memory and a write cycle from a shared bus system side on the local shared memory is reduced and a memory LSI which may be used in such unit are provided. The parallel processing system comprises a local shared memory between the processor and a shared bus. Address and data input means (WA and DI) for writing data to a memory cell and address input means (RA) and data output means (DO) for reading data are provided independently from each other to parallelize operations for reading from the processor side and for writing from the shared bus side.

Abstract: A processor for constructing a single processor system or multiprocessor system comprises, within a base processor element constituting the processor, two CPU with associated local memories, a dual-port RAM accessible from said CPUs, and a common bus switch circuit for connecting any one of said CPUs to a common bus shared by said CPUs.

Abstract: A parallel processing system in which access contention of a read cycle from a processing unit side to a local shared memory and a write cycle from a shared bus system side on the local shared memory is reduced and a memory LSI which may be used in such unit are provided. The parallel processing system comprises the local shared memory between the processor and a shared bus. Address and data input means (WA and DI) for writing data to a memory cell and address input means (RA) and data output means (DO) for reading data are provided independently from each other to parallelize operations for reading from the processor side and for writing from the shared bus side.

Abstract: Prevention of reduction in the production yield due to the increase in the area of a semiconductor chip permits a sophisticated-performance single-chip semiconductor device to be fabricated. This also permits a many-kind small-amount production of semiconductor devices to be implemented. After plural semiconductor chips 2 and 3 are fabricated separately, only defect-free chips of them are selected. The selected defect-free chips are connected in contact between their side walls of their densest faces of atoms of their substrates so that the surfaces 4a and 4b where elements are to be formed are located in the same plane. Thus, even when the chip area is increased, reduction of the production yield can be prevented, thereby permitting a large-area sophisticated-performance single chip semiconductor device to be fabricated.

Abstract: A memory system which includes a memory array having a column address input and a page address input, addressed by a column pointer and a page pointer; a processor for accessing the memory array with employment of a data bus and an address bus in response to an access instruction; a page register unit coupled to the processor, for storing therein a page address and a first offset address, which are received from the processor via the data bus; a page address counter unit coupled to the page register unit for performing a predetermined calculation to the page address by utilizing the first offset address; a column register unit coupled to the processor, for storing therein a column address and a second offset address, which are received via the address bus from the processor; a column address counter unit coupled to the column register unit, for performing a preselected calculation to the column address with employment of the second offset address; and an address latch unit coupled to the page address counter

Abstract: A communication control apparatus includes a pair of communication controllers each having a dual port RAM (DPR) with an interruption request generating function. A master processor system is connected to one port of the DPR in one of the communication controllers. A slave processor system is connected to one port of the DPR in the other communication controller. A channel controller is connected to each of the other port of the DPR in one communication controller and to the other port of the other communication controller, respectively. Both of the channel controllers are coupled by a communication channel. Both of the communication controllers mutually transfer data on the communication channel so that the contents of the DPR in the pair of communication controllers always coincide, so that the master processor system and the slave processor system operate as if they were connected by one DPR.

Abstract: A circuit board includes a circuit-conductor layer, a ground layer and a power source layer superposed in a multilayer form through dielectric layers therebetween. A heat conduction through inside of the circuit board is enhanced so that circuit chips mounted on the circuit board can be cooled down to a level capable of operating normally. The circuit board can be formed to be compact. In order to enhance the heat transfer in the circuit board, at least one of the ground layer and power source layer is formed in a multilayer manner. It is preferable to form these layers at a thickness larger than that of the circuit-conductor layer. Further, preferably, the pin of the chip mounted on the board and at least one of the ground layer and power supply layer are connected to each other in such a manner as to enhance the heat conduction.

Abstract: A processor for constructing a single processor system or multiprocessor system comprises, within a base processor element constituting the processor, two CPU with associated local memories, a dual-port RAM accessible from said CPUs, and a common bus switch circuit for connecting any one of said CPUs to a common bus shared by said CPUs.

Abstract: A processor system includes an external resource, and a main CPU with a built-in bus control mechanism outputting an address bus and control signals and having a function to access the external resource and input and output necessary data through a data bus. The external resource includes a plurality of external resources. Controllers for outputting control signals and address signals to access the external resources by using a plurality of address strobe signals from the main CPU are provided for the external resources, respectively. The external resources input and output data with the main CPU through the data bus by the signals from the controllers. Real time processing for the respective types of instructions is attained.

Abstract: A hierarchical structure processor including a memory for storing processing instruction code data described sequentially; a main CPU for fetching and decoding the processing instruction code data and generating an executing sequence, the main CPU having buses for transferring instructions, data control signals; and a plurality of sub CPUs connected to the main CPU through the buses for executing basic instructions received from the main CPU. The main CPU includes a bus controller for sending a macro instruction indicative of the basic processing to one of the sub CPUs and for receiving an execution result of the processing designated by the macro instruction from the sub CPU. The bus controller waits for a READY signal from the associated sub CPU having the execution result.

Abstract: When a plurality of processors share a plurality of tasks and parallelly process the shared tasks, each of these processors outputs bit information for designating a processor in a group to which the processor belongs, when a currently executed task processing has been terminated, and the bit information is stored in a synchronous register disposed in each of the processors. When it is detected that all of processors in the same group have terminated task processings, each of these processors in the same group are supplied with a synchronization termination signal from the synchronous registers related thereto. Before all of the task processings have been terminated in the same group, any processors in the same group which have already terminated their task processings progress the execution of the next tasks until they access for the first time a data sharing circuit for holding data shared among the processors.

Abstract: A memory device comprises a dynamic random access memory (DRAM) organized by page and a memory access devices. The DRAM corresponding to the pages is divided into a plurality of groups each constituted of pages for storing data which are unlikely to give rise to interference between pages. The DRAM of each group is constituted as a memory system which responds to page access. The memory access devices are provided separately for the memory system of each group. Each memory access device has a memory means which, in response to an access designating a page address of the memory system associated therewith, stores an old page address designated at least one access earlier, and judging means which, in response to said page address access, judges whether or not the new page address designated by said access coincides with said old page address stored in said storage means.