Patents by Inventor Masaya Kibune
Masaya Kibune has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11138505Abstract: A method of generating a neural network may be provided. A method may include applying non-linear quantization to a plurality of synaptic weights of a neural network model. The method may further include training the neural network model. Further, the method ma include generating a neural network output from the trained neural network model based on or more inputs received by the trained neural network model.Type: GrantFiled: December 21, 2017Date of Patent: October 5, 2021Assignee: FUJITSU LIMITEDInventors: Masaya Kibune, Xuan Tan
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Publication number: 20190197395Abstract: A method of generating a model ensemble may be provided. A method may include training a base model including a plurality of layers. The method may also include generating a plurality of models for the neural network based on the base model. Each model of the plurality of models includes a plurality of layers. Further, the method may include modifying a layer of each of the plurality of models such that each model of the plurality of models includes a layer modified with respect to an associated layer of each of the base model and each of the other plurality of models. In addition, the method may include tuning each modified layer of the plurality of models.Type: ApplicationFiled: December 21, 2017Publication date: June 27, 2019Applicant: FUJITSU LIMITEDInventors: Masaya KIBUNE, Xuan TAN
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Publication number: 20190197408Abstract: A method of generating a neural network may be provided. A method may include applying non-linear quantization to a plurality of synaptic weights of a neural network model. The method may further include training the neural network model. Further, the method ma include generating a neural network output from the trained neural network model based on or more inputs received by the trained neural network model.Type: ApplicationFiled: December 21, 2017Publication date: June 27, 2019Applicant: FUJITSU LIMITEDInventors: Masaya KIBUNE, Xuan TAN
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Publication number: 20170359153Abstract: A method of measuring linearity characteristics of a delay line may be provided. The method may include generating an output signal from a receiver including a delay line. The method may also include measuring linearity characteristics of the delay line based on a target performance parameter of the output signal.Type: ApplicationFiled: June 14, 2016Publication date: December 14, 2017Applicant: FUJITSU LIMITEDInventors: Daisuke USUI, Masaya KIBUNE, Nikola NEDOVIC
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Patent number: 9509327Abstract: An A/D converter includes an A/D conversion unit, a histogram generation-storage unit, and a control unit. The A/D conversion unit is configured to receive an input voltage, perform an analog-to-digital conversion, and output digital data, and the histogram generation-storage unit is configured to receive the digital data, generate a histogram for a waveform of the input voltage, and store the generated histogram therein. The control unit is configured to control an analog-to-digital conversion characteristics of the A/D conversion unit, based on the histogram stored in the histogram generation-storage unit.Type: GrantFiled: February 16, 2016Date of Patent: November 29, 2016Assignee: FUJITSU LIMITEDInventors: Masaya Kibune, Sanroku Tsukamoto
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Publication number: 20160173114Abstract: An A/D converter includes an A/D conversion unit, a histogram generation-storage unit, and a control unit. The A/D conversion unit is configured to receive an input voltage, perform an analog-to-digital conversion, and output digital data, and the histogram generation-storage unit is configured to receive the digital data, generate a histogram for a waveform of the input voltage, and store the generated histogram therein. The control unit is configured to control an analog-to-digital conversion characteristics of the A/D conversion unit, based on the histogram stored in the histogram generation-storage unit.Type: ApplicationFiled: February 16, 2016Publication date: June 16, 2016Applicant: FUJITSU LIMITEDInventors: Masaya KIBUNE, Sanroku TSUKAMOTO
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Patent number: 9118451Abstract: A receiver circuit includes: an input ADC configured to convert an input data signal to sample data in accordance with a clock; a boundary phase computation circuit configured to determine the boundary phase of the input data signal based on the sample data; an eye pattern computation circuit configured to compute a maximum amplitude phase of an eye pattern of the input data signal based on the sample data and the boundary phase; and a determination circuit configured to determine a value of the input data signal in the maximum amplitude phase based on the sample data and the maximum amplitude phase.Type: GrantFiled: February 25, 2014Date of Patent: August 25, 2015Assignee: Fujitsu LimitedInventors: Masaya Kibune, Hirotaka Tamura
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Publication number: 20140376675Abstract: A receiver circuit includes: an input ADC configured to convert an input data signal to sample data in accordance with a clock; a boundary phase computation circuit configured to determine the boundary phase of the input data signal based on the sample data; an eye pattern computation circuit configured to compute a maximum amplitude phase of an eye pattern of the input data signal based on the sample data and the boundary phase; and a determination circuit configured to determine a value of the input data signal in the maximum amplitude phase based on the sample data and the maximum amplitude phase.Type: ApplicationFiled: February 25, 2014Publication date: December 25, 2014Applicant: FUJITSU LIMITEDInventors: Masaya KIBUNE, Hirotaka TAMURA
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Patent number: 8798568Abstract: A signal transmission method suppresses a reflected wave of a transmission signal on a transmission line, by obtaining level and time information related to the reflected wave by computing a correlation between a data pattern of the transmission signal and the reflected wave, and correcting a waveform of the transmission signal based on the level and time information related to the reflected wave.Type: GrantFiled: September 18, 2009Date of Patent: August 5, 2014Assignee: Fujitsu LimitedInventor: Masaya Kibune
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Patent number: 8797076Abstract: A duty ratio correction circuit, includes: a frequency divider configured to output a second clock signal having a first level that is inverted at a timing of a first edge of a first clock signal and a third clock signal having a second level that is inverted at a timing of a second edge of the first clock signal; phase interpolator configured to generate a fourth clock signal and a fifth clock signal based on phase interpolation of any two of the second clock signal, the third clock signal, a first inverted signal that is obtained by inverting the second clock signal, or a second inverted signal that is obtained by inverting the third clock signal; and a multiplier configured to output an exclusive OR signal of the fourth clock signal and the fifth clock signal as a sixth clock signal.Type: GrantFiled: May 31, 2013Date of Patent: August 5, 2014Assignee: Fujitsu LimitedInventor: Masaya Kibune
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Patent number: 8634454Abstract: A receiver circuit includes: an equalization circuit that equalizes a first signal to obtain a second signal, and adjusts a characteristic of an equalization in accordance with an error between the second signal and a third signal; and a first offset adjustment circuit that adjusts an offset of the first signal in accordance with an error signal indicating the error.Type: GrantFiled: June 29, 2010Date of Patent: January 21, 2014Assignee: Fujitsu LimtedInventors: Masaya Kibune, Hirotaka Tamura
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Publication number: 20130328602Abstract: A duty ratio correction circuit, includes: a frequency divider configured to output a second clock signal having a first level that is inverted at a timing of a first edge of a first clock signal and a third clock signal having a second level that is inverted at a timing of a second edge of the first clock signal; phase interpolator configured to generate a fourth clock signal and a fifth clock signal based on phase interpolation of any two of the second clock signal, the third clock signal, a first inverted signal that is obtained by inverting the second clock signal, or a second inverted signal that is obtained by inverting the third clock signal; and a multiplier configured to output an exclusive OR signal of the fourth clock signal and the fifth clock signal as a sixth clock signal.Type: ApplicationFiled: May 31, 2013Publication date: December 12, 2013Inventor: Masaya KIBUNE
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Publication number: 20130314142Abstract: A phase-combining circuit for combining cyclic timing waveforms that have been phase-controlled by control signals based on three or more input signals of different phases, has a weight signal generating circuit and a weighting circuit. The weight signal generating circuit generates weights according to the control signals, and the weighting circuit gives the weights to the respective input signals, with a positive or negative polarity for each one signal.Type: ApplicationFiled: July 24, 2013Publication date: November 28, 2013Applicant: FUJITSU LIMITEDInventors: Hirotaka TAMURA, Masaya KIBUNE
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Patent number: 8588359Abstract: A reception circuit includes: an AD converter; an equalization circuit that equalizes an output of the AD converter; a determination circuit to which error information is input from the equalization circuit; and a controller that adjusts at least one of resolution and voltage range of the AD converter, in the circuit the determination circuit outputs a control signal to adjust at least one of resolution and voltage range to the controller based on the error information.Type: GrantFiled: April 9, 2010Date of Patent: November 19, 2013Assignee: Fujitsu LimitedInventor: Masaya Kibune
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Patent number: 8319542Abstract: An integrated circuit includes a bypass signal path exchanging, between transceivers which are included in the integrated circuit, a signal transmitted/received between a transceiver of the transceivers and an internal logic circuit which processes data being input/output by transceiver with bypassing the internal logic circuit, a switch switching a pathway of the bypass signal path, and a switch changeover controller transferring a switch control signal that performs a changeover of the switch.Type: GrantFiled: September 29, 2006Date of Patent: November 27, 2012Assignee: Fujitsu LimitedInventors: Hirotaka Tamura, Masaya Kibune
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Patent number: 8320503Abstract: A receiver that receives a train of a plurality of symbols representing digital data, includes: an isolated pulse detector that detects whether the digital data includes an isolated pulse in the symbol train, respectively; a phase detector that detects a timing at which the level of the symbols changes; a symbol value converter that converts the symbols into logical values on the basis of the timing detected by the phase detector; and a data selector that selects a logical value of the isolated pulse instead of the logical value converted by the symbol value converter when the isolated pulse detector detects the digital data containing the isolated pulse.Type: GrantFiled: March 24, 2010Date of Patent: November 27, 2012Assignee: Fujitsu LimitedInventors: Hirotaka Tamura, Masaya Kibune
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Patent number: 8299948Abstract: A receiving circuit includes: a clock generating circuit to generate a plurality of clock signals in a cycle; an oversampling circuit to oversample input data based on the plurality of clock signals and output a plurality of samples of digital data in a unit interval; a data boundary determining circuit to detect a changing point of the digital data, determine data boundaries of the unit interval based on the changing point, and output digital data corresponding to a central data between the data boundaries; and a clock phase control circuit to control a phase of at least one of the plurality of clock signals so that a first number of the plurality of samples becomes a certain value when a second number of samples between the data boundaries is larger than a threshold value.Type: GrantFiled: February 9, 2011Date of Patent: October 30, 2012Assignee: Fujitsu LimitedInventors: Takayuki Shibasaki, Masaya Kibune, Takuji Yamamoto
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Patent number: 8238504Abstract: A clock generation circuit includes: a first determination circuit that detects an input signal at a first phase position based on first frequency signal; a second determination circuit that detects the input signal at a second phase position based on second frequency signal; a phase detector that compares output of the first determination circuit and output of the second determination circuit; a first summing circuit which sums comparison result and first control signal; a second summing circuit which sums comparison result and second control signal; a first voltage controlled oscillation circuit which receives output of the first summing circuit and outputs the first frequency signal; a second voltage controlled oscillation circuit which received output of the second summing circuit and outputs the second frequency signal; and a phase adjustment circuit which generates first control signal and second control signal based on first frequency signal and second frequency signal.Type: GrantFiled: December 8, 2009Date of Patent: August 7, 2012Assignee: Fujitsu LimitedInventors: Yasumoto Tomita, Masaya Kibune, Hirotaka Tamura
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Patent number: 8031091Abstract: A reception circuit includes: an AD converter that outputs digital data in accordance with an input signal; a correction circuit that corrects nonlinearity of the AD converter; and an equalization circuit that equalizes the corrected digital data, wherein the correction circuit includes: a conversion table used to convert digital data output from the AD converter; and a correction amount computation circuit that creates the conversion table from the output data of the AD converter and the output of the equalization circuit. The correction amount computation circuit creates the conversion table so that there is no dependence between the ADC output value of the AD converter and the estimation result by the equalization circuit for the ADC output value.Type: GrantFiled: April 9, 2010Date of Patent: October 4, 2011Assignee: Fujitsu LimitedInventor: Masaya Kibune
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Publication number: 20110221491Abstract: A receiving circuit includes: a clock generating circuit to generate a plurality of clock signals in a cycle; an oversampling circuit to oversample input data based on the plurality of clock signals and output a plurality of samples of digital data in a unit interval; a data boundary determining circuit to detect a changing point of the digital data, determine data boundaries of the unit interval based on the changing point, and output digital data corresponding to a central data between the data boundaries; and a clock phase control circuit to control a phase of at least one of the plurality of clock signals so that a first number of the plurality of samples becomes a certain value when a second number of samples between the data boundaries is larger than a threshold value.Type: ApplicationFiled: February 9, 2011Publication date: September 15, 2011Applicant: FUJITSU LIMITEDInventors: Takayuki SHIBASAKI, Masaya Kibune, Takuji Yamamoto