Patents by Inventor Masaya Muranaka
Masaya Muranaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6064605Abstract: Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Further, a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor to write the same write signal. Two dynamic memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode to associate a state in which an electric charge exists in a capacitor of each dynamic memory cell with a logic 1 of a read signal and associate a state in which no electric charge exists in the capacitor with a logic 0 of the read signal in response to a write operation. Thus, the logics 1 of the two read signals are preferentially output.Type: GrantFiled: September 14, 1999Date of Patent: May 16, 2000Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Masaya Muranaka, Shinichi Miyatake, Yukihide Suzuki, Kanehide Kenmizaki, Makoto Morino, Tetsuya Kitame
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Patent number: 5969996Abstract: Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Further, a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor to write the same write signal. Two dynamic memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode to associate a state in which an electric charge exists in a capacitor of each dynamic memory cell with a logic 1 of a read signal and associate a state in which no electric charge exists in the capacitor with a logic 0 of the read signal in response to a write operation. Thus, the logics 1 of the two read signals are preferentially output.Type: GrantFiled: August 31, 1998Date of Patent: October 19, 1999Assignee: Hiachi, Ltd.Inventors: Masaya Muranaka, Shinichi Miyatake, Yukihide Suzuki, Kanehide Kenmizaki, Makoto Morino, Tetsuya Kitame
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Patent number: 5818784Abstract: Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Further, a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor to write the same write signal. Two dynamic memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode to associate a state in which an electric charge exists in a capacitor of each dynamic memory cell with a logic 1 of a read signal and associate a state in which no electric charge exists in the capacitor with a logic 0 of the read signal in response to a write operation. Thus, the logics 1 of the two read signals are preferentially output.Type: GrantFiled: April 26, 1996Date of Patent: October 6, 1998Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Masaya Muranaka, Shinichi Miyatake, Yukihide Suzuki, Kanehide Kenmizaki, Makoto Morino, Tetsuya Kitame
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Patent number: 5805513Abstract: A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.Type: GrantFiled: May 2, 1995Date of Patent: September 8, 1998Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Yasushi Takahashi, Hidetoshi Iwai, Satoshi Oguchi, Hisashi Nakamura, Hiroyuki Uchiyama, Toshitugu Takekuma, Shigetoshi Sakomura, Kazuyuki Miyazawa, Masamichi Ishihara, Ryoichi Hori, Takeshi Kizaki, Yoshihisa Koyama, Haruo Ii, Masaya Muranaka, Hidetomo Aoyagi, Hiromi Matsuura
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Patent number: 5726994Abstract: A memory array is logically and/or physically divided into a plurality of blocks to allow test by individual blocks. When a plurality of column address strobe signals are provided and memory accessing is made by a plurality of bits to the memory array corresponding to the column address strobe signal, tests are independently conducted for each memory array by using the column address strobe signal.Type: GrantFiled: February 29, 1996Date of Patent: March 10, 1998Assignees: Hitachi, Ltd., Texas Instruments IncorporatedInventors: Hiromi Matsuura, Masaya Muranaka, Yasunori Orito
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Patent number: 5598373Abstract: A defect remedy LSI mounted on a memory module, comprising: an input interface portion for capturing address and control signals, the input interface portion being the same as that of a dynamic RAM; an input/output interface portion corresponding to a data bus of a memory device comprised of a plurality of dynamic random access memories; a memory circuit to which a chip address and an X defective address of any of the plurality of random access memories are electrically written, the memory circuit being substantially made nonvolatile; a redundancy remedy RAM portion composed of a static RAM wherein a word line is selected by a compare match signal between an X address signal and the defective address of the memory circuit, the X address signal and the defective address being captured via the input interface portion, and a column is selected by a Y address signal captured via the input interface portion; a selecting portion for connecting a data input/output bus of the redundancy remedy RAM portion to an inputType: GrantFiled: June 7, 1995Date of Patent: January 28, 1997Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Shoji Wada, Kanehide Kenmizaki, Masaya Muranaka, Masahiro Ogata, Hidetomo Aoyagi, Tetsuya Kitame, Masahiro Katayama, Shoji Kubono, Yukihide Suzuki, Makoto Morino, Sinichi Miyatake, Seiichi Shundo, Yoshihisa Koyama, Nobuhiko Ohno
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Patent number: 5596537Abstract: A semiconductor device test circuit for inclusion on a semiconductor chip having a semiconductor device thereon, wherein a test mode with respect to the semiconductor device is not entered during normal use of the semiconductor device and the test mode can be entered without applying a voltage higher than the power supply voltage to an external terminal of the semiconductor device. The test circuit includes a decoder circuit which detects the matching of a first address input corresponding to a test mode, and a latch circuit which latches the signal indicating the matching of the first address input with a test mode. A second decoder circuit then detects the matching of a second address to the test mode, the second address being input when the matching signal for the first address has been latched. A second latch circuit latches the signal indicating the matching of the second address. A third address input is processed by a third decoder circuit and a third latch circuit in the same way.Type: GrantFiled: July 14, 1994Date of Patent: January 21, 1997Assignees: Texas Instruments Incorporated, Hitachi Ltd.Inventors: Shunichi Sukegawa, Shiyuzo Shiozaki, Hiromi Matsuura, Masaya Muranaka
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Patent number: 5485425Abstract: There is provided a semiconductor memory device having a redundant column. This memory device has a redundant column disposed in the direction of the Y-system address, a ROM accessed by using an X-system address, a Y-system address signal having a defective cell included in the cells therein being electrically written into the ROM, a comparator circuit for comparing a signal read out from this ROM with a Y-system address signal and outputting a coincidence signal upon coincidence, and a defect relieving circuit responsive to output of the coincidence signal from this comparator circuit to cause selection of the redundant column of Y system instead of the Y-system address selection device.Type: GrantFiled: January 20, 1995Date of Patent: January 16, 1996Assignees: Hitachi, Ltd., Texas Instruments IncorporatedInventors: Hidetoshi Iwai, Masaya Muranaka, Takumi Nasu, Shunichi Sukegawa
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Patent number: 5426613Abstract: A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.Type: GrantFiled: November 6, 1992Date of Patent: June 20, 1995Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Yasushi Takahashi, Hidetoshi Iwai, Satoshi Oguchi, Hisashi Nakamura, Hiroyuki Uchiyama, Toshitugu Takekuma, Shigetoshi Sakomura, Kazuyuki Miyazawa, Masamichi Ishihara, Ryoichi Hori, Takeshi Kizaki, Yoshihisa Koyama, Haruo Ii, Masaya Muranaka, Hidetomo Aoyagi, Hiromi Matsuura
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Patent number: 5301142Abstract: Each of a plurality of memory arrays is divided into a plurality of memory mats MAT00L-MAT07L to MAT10R-MAT17R in directions in which word lines and bit lines extend. First common data lines, that is, sub-IO lines, are provided which correspond to these memory mats and which are disposed in parallel to the word lines. Bit lines designating the corresponding memory mats are selectively connected to the first common data lines. Second common data lines, that is, main IO line groups MIOG0-MIOG7, are also provided and are disposed in parallel to the bit lines. Designated sub-IO lines are selectively connected to the second common data lines. Moreover, a plurality of main amplifiers forming a main amplifier unit MAU0 are orderly arranged in the direction in which the bit lines extend.Type: GrantFiled: June 8, 1992Date of Patent: April 5, 1994Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Yukihide Suzuki, Masaya Muranaka, Hiromi Matsuura, Yoshinobu Nakagome, Hitoshi Tanaka, Eiji Yamasaki, Toshiyuki Sakuta
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Patent number: 5287000Abstract: According to one aspect of the present invention, a semiconductor chip, which can be mounted in a zigzag in-line type package (ZIP) partially using a tabless lead frame, includes bonding pads arranged on the chip so that the chip can be applied also to other different types of packages. These different types of packages include a small out-line J-bent type package (SOJ) which uses a lead frame with tab, and a dual in-line type package (DIP) which uses a tabless lead frame. Further, a plurality of bonding pad pairs are provided amongst the bonding pads on the chip, each pad of such bonding pad pairs having the same function as the other pad associated therewith thereby duplicating a common function in different bonding pads on the semiconductor chip so as to make the semiconductor chip compatible with a variety of or different types of packages.Type: GrantFiled: March 26, 1991Date of Patent: February 15, 1994Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Yasushi Takahashi, Kazuyuki Miyazawa, Hidetoshi Iwai, Masaya Muranaka, Yoshitaka Kinoshita, Satoru Koshiba
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Patent number: 5217917Abstract: A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.Type: GrantFiled: March 20, 1990Date of Patent: June 8, 1993Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Yasushi Takahashi, Hidetoshi Iwai, Satoshi Oguchi, Hisashi Nakamura, Hiroyuki Uchiyama, Toshitugu Takemuma, Shigetoshi Sakomura, Kazuyuki Miyazawa, Masamichi Ishihara, Ryoichi Hori, Takeshi Kizaki, Yoshihisa Koyama, Haruo Ii, Masaya Muranaka, Hidetomo Aoyagi, Hiromi Matsuura
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Patent number: 5151772Abstract: A semiconductor integrated circuit device is provided which includes a memory cell array located in a generally central area of a semiconductor substrate with peripheral circuits located at both ends of the semiconductor substrate. A wiring layer is also provided which couples the peripheral circuits to one another. This wiring layer is arranged to have a double-layer structure of first and second aluminum layers which are electrically coupled to one another.Type: GrantFiled: November 20, 1990Date of Patent: September 29, 1992Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Yasushi Takahashi, Hiromi Matsuura, Yoshihisa Koyama, Masaya Muranaka, Katsutaka Kimura, Kazuyuki Miyazawa, Masamichi Ishihara, Hidetoshi Iwai
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Patent number: 5021998Abstract: Disclosed are measurement (observation) pads for judging whether or not a dynamic random access memory (DRAM) adopting a shared sense system is functioning as designed. Concretely, measurement pads are formed by the step of forming a second layer of wiring respectively connected to pairs of complementary data lines which are formed by the step of forming a first layer of wiring, and the signal waveforms of the pairs of complementary data lines are measured using the measurement pads. Further, the measurement pads are provided between wiring layers which become fixed potentials in, at least, the operation of measuring data. In addition, each of the measurement pads is used in common by data lines which are respectively connected to two memory cells located in different memory cell mats.Type: GrantFiled: April 18, 1989Date of Patent: June 4, 1991Assignees: Hitachi, Ltd., Hitachi VLSI EngineeringInventors: Yukihide Suzuki, Masaya Muranaka, Masamichi Ishihara
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Patent number: 4934820Abstract: According to the present invention, a semiconductor chip is mounted on a zigzag in-line type package (ZIP) partially using a tabless lead frame and bonding pads are arranged on the chip so that the chip can be applied also to other different types of packages. As different types of packages there are a small out-line J-bent type package (SOJ) for which there is used a lead frame with tab and a dual in-line type package (DIP) for which there is used a tabless lead frame. Further, a plurality of bonding pad pairs are provided among the bonding pads on the chip each pad of such bonding pad pairs having the same function as the other pad associated therewith thereby duplicating a common function in different bonding pads on the semiconductor chip so as to readily facilitate, or make compatible, the semiconductor chip to a variety of or different types of packages.Type: GrantFiled: October 12, 1988Date of Patent: June 19, 1990Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Yasushi Takahashi, Kazuyuki Miyazawa, Hidetoshi Iwai, Masaya Muranaka
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Patent number: 4849939Abstract: A semiconductor memory having a memory array, a first and a second selection line which are connected to a memory cell, and a selection means which selects either one of the selection lines. The selection means includes a selection circuit which optionally selects the first selection line or the second selection line when an address signal corresponding to the first selection line is aligned with a predetermined address signal.Type: GrantFiled: September 24, 1987Date of Patent: July 18, 1989Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Masaya Muranaka, Hiromi Matsuura, Kanehide Kenmizaki, Osamu Okayama
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Patent number: 4807190Abstract: A dynamic RAM is provided in which an output voltage of a booster circuit for forming a word line selection timing signal is rendered greater than a power source potential and less than a predetermined potential by providing voltage limitation means, thereby preventing destruction of circuit elements receiving the output voltage.Type: GrantFiled: February 24, 1987Date of Patent: February 21, 1989Assignees: Hitachi Ltd., Hitachi VLSI Engineering Corp.Inventors: Kyoko Ishii, Kazumasa Yanagisawa, Masaya Muranaka