Abstract: A circuit for automatically adjusting duty cycle of an output clock signal is provided.

Abstract: An IC memory testing apparatus comprises a pattern generating circuit, a decision circuit, a first-in memory circuit which stores the defect data of a IC memory under test and simultaneously reads the resulting data. A latch circuit is also used to shorten the testing time. The resulting information about the defective cell of the tested IC memory is stored and read out during the test, with the memory circuit executing a storing operation for the address of defective cell data and simultaneously executing a reading operation for the data having been stored. The time periods required for the reading and writing operations are set independently of each other, and the operation frequency of the memory circuit is less than for testing the memory to be tested.

Abstract: A test signal generating circuit for generating a test signal for testing logic circuits comprises four delay units each including a setting circuitry for setting a delay time, a gate and a counter for counting clock pulses in number corresponding to the delay time placed in the setting circuitry. The output signals of two delay units are applied to a flip-flop as set input signals, while the output signals of the other two delay units are applied to the flip-flop as reset input signals, whereby the timing and/or waveform of the test signal outputted by the flip-flop is varied in dependence on the values placed in the setting circuitries.

Abstract: A pattern generating apparatus for testing IC device includes an input/output mode memory, a pattern memory storing a driver pattern and an expected pattern, a driver pattern generator for outputting the driver pattern in response to the outputs of the pattern memory and the input/output mode memory, and an expected pattern generator for generating the expected pattern. The driver pattern is applied to the IC device whose output pattern is compared with the expected pattern in a comparison/decision circuit to decide whether the IC device is to be satisfactory or not. The pattern memory is of two-bit structure so that the driver pattern and the expected pattern can be varied in respect to the waveform in dependence on combinations of the two bits.