Abstract: A computer system has a central processing unit (“CPU”) and a plurality of peripheral devices. A bus interconnects the CPU and the peripheral devices. Command signals are transmitted over the bus including an initiator ready signal (“IRDY”), a device select signal (“DEVSEL”) and a target ready signal (“TRDY”). First and second direct memory access devices (“DMA”) are connected to the bus and assigned the same address space. First and second switches selectively connect and disconnect the DEVSEL and TRDY signals that are output from the first and second DMA devices, respectively. Controller logic receives the DEVSEL and TRDY signals and directs the opening and closing of the first and second switches.

Abstract: An information processing system that can reduce the operating frequency of a CPU, or halt the operation of the CPU, at an adequate timing, even when the system is engaged in exchanging data with another independent apparatus (e.g., another PC) via a communication port (a serial port or a parallel port), or when a communication application is being executed.

Abstract: A computer system has a central processing unit ("CPU") and a plurality of peripheral devices. A bus interconnects the CPU and the peripheral devices. Command signals are transmitted over the bus including an initiator ready signal ("IRDY"), a device select signal ("DEVSEL"), and a target ready signal ("TRDY"). First and second direct memory access devices ("DMA") are connected to the bus and assigned the same address space. First and second switches selectively connect and disconnect the DEVSEL and TRDY signals that are output from the first and second DMA devices, respectively. Controller logic receives the DEVSEL and TRDY signals and directs the opening and closing of the first and second switches.

Abstract: An information processing system which has (a) a CPU that is operated in a normal mode during which the CPU is driven at a relatively fast operating clock rate, and a power saving mode during which the operating clock has a lower rate or is halted; (b) at least one peripheral device; (c) a bus for performing communication between the CPU and the peripheral device; (d) a termination detector detecting a completion of a predetermined transaction between the CPU and the peripheral device; (e) a time counter measuring a predetermined period of time after the completion of the predetermined transaction; and (f) a power saving control causing the CPU enter the power saving mode until the time counted by the time counting means reaches the predetermined period of time.

Abstract: Disclosed is a computer system that includes a CPU that can be operated both in a normal mode and in a power saving mode. The system further includes at least one peripheral device and a bus for allowing communication between the CPU and the peripheral device. A bus cycle detector monitors a bus cycle on the bus and a condition determiner determines the operation mode for the CPU in a specific bus cycle that is detected by the bus cycle detector. A signal generator is used to provide to the CPU, a control signal for changing the CPU's operation mode in accordance with a determination result obtained by the condition determiner. The disclosed system can reduce the operating frequency of a CPU or halt the operation of the CPU in accordance with an appropriate timing even when asynchronous communication is performed with peripheral devices.

Abstract: A foundation composition useful in making-up a mannequin, comprising a polymeric film-forming material, a water-insoluble white powder material, the particles of which have an average size of from 2 to 100 microns and the content of which is in a range of from 20 to 60% based on the entire weight of the composition, and water. A method for making up said mannequin comprising undercoating the skin of said mannequin with said composition and a mannequin product of said method are claimed.