Patents by Inventor Masayoshi Tomita

Masayoshi Tomita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5281835
    Abstract: A semi-custom integrated circuit comprises a basic cell array comprising a plurality of basic cells aligned in a first direction, the basic cells comprising a transistor unit, a capacitor unit and a resistor unit arranged in a second direction perpendicular to the first direction. The transistor unit is positioned between the capacitor unit and the resistor unit. The transistor unit has a terminal portion for connection of wiring, the capacitor unit having a terminal portion for connection of wiring, the resistor unit having a terminal portion for connection of wiring. The terminal portions of said transistor unit, capacitor unit and resistor unit are aligned along a line.
    Type: Grant
    Filed: January 27, 1992
    Date of Patent: January 25, 1994
    Assignee: Fujitsu Limited
    Inventors: Masayoshi Tomita, Tadahiro Saitoh, Kiyokazu Hasegawa, Noboru Kosugi
  • Patent number: 4516312
    Abstract: A method for constructing delay circuits in a master slice IC formed on a semiconductor substrate. The master slice IC comprises regularly arranged MIS transistors having gate electrodes. The MIS transistors includes various logic circuits. A delay circuit is formed between two logic circuits. The delay circuit comprises a resistor and a capacitor. The resistor is constructed using the resistances of the gate electrodes by sequentially connecting the gate electrodes between two logic circuits. The capacitor is constructed using capacitances formed between the gate electrodes and the semiconductor substrate. A precise delay time of a delay circuit having a small area can be obtained.
    Type: Grant
    Filed: February 10, 1982
    Date of Patent: May 14, 1985
    Assignee: Fujitsu Limited
    Inventor: Masayoshi Tomita
  • Patent number: 4369381
    Abstract: A CMOS Schmitt-trigger circuit for shaping the wave form of an input signal to be applied to logic circuits, such as flip-flops, counters, etc. The CMOS Schmitt-trigger circuit has an input terminal connected to a signal source, and comprises a first CMOS inverter, a second CMOS inverter connected in cascade to the first CMOS inverter, a third CMOS inverter connected in cascade to the second CMOS inverter, and a feedback resistance connected between the output end of the third CMOS inverter and the input end of the second CMOS inverter. The schmitt width of the CMOS Schmitt inverter according to the present invention has less dependency on the impedance of the input signal source than the prior-art devices do.
    Type: Grant
    Filed: July 11, 1980
    Date of Patent: January 18, 1983
    Assignee: Fujitsu Limited
    Inventors: Keizo Okamoto, Masayoshi Tomita, Osamu Takagi