Patents by Inventor Masayuki Ezawa

Masayuki Ezawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8248483
    Abstract: A signal processing apparatus according to the present invention includes: a common pre-processing section for performing signal processing common to a photographed image process and a flicker detection process on an input image signal; a photographed image processing section for performing image signal processing for a displayed image on an image signal from the common pre-processing section; a flicker detection pre-processing section for performing image signal processing for flicker detection on the image signal from the common pre-processing section; and a flicker detecting section for performing flicker detection based on the image signal from the flicker detection pre-processing section.
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: August 21, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masayuki Ezawa, Masayuki Shinagawa, Toshihiro Akamatsu
  • Publication number: 20090316020
    Abstract: A signal processing apparatus according to the present invention includes: a common pre-processing section for performing signal processing common to a photographed image process and a flicker detection process on an input image signal; a photographed image processing section for performing image signal processing for a displayed image on an image signal from the common pre-processing section; a flicker detection pre-processing section for performing image signal processing for flicker detection on the image signal from the common pre-processing section; and a flicker detecting section for performing flicker detection based on the image signal from the flicker detection pre-processing section.
    Type: Application
    Filed: June 17, 2009
    Publication date: December 24, 2009
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Masayuki Ezawa, Masayuki Shinagawa, Toshihiro Akamatsu
  • Patent number: 7453489
    Abstract: An image processing apparatus of the present invention is provided with (a) reduction calculation sections for reducing the number of a plurality of input image data, corresponding to a plurality of images that satisfy azimuth difference relations each other, in a lateral direction, (b) a three-dimensional processing section for combining the image data that have been reduced the number by the reduction calculation sections so as to prepare a three-dimensional image data; and (c) a display switching control section for switching and selecting which one of three-dimensional image data prepared by the three-dimensional processing section and two-dimensional image data prepared by using one of the plurality of input image data should be outputted from the image processing apparatus.
    Type: Grant
    Filed: February 6, 2004
    Date of Patent: November 18, 2008
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Masayuki Ezawa
  • Patent number: 7397511
    Abstract: In a folding information terminal device capable of taking a three-dimensional image and including two planes which become opposite to each other when the folding information terminal device is folded; there is provided at least one image pickup section on one plane of the two planes, and at least one image pickup section on the other plane.
    Type: Grant
    Filed: January 12, 2004
    Date of Patent: July 8, 2008
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Masayuki Ezawa
  • Patent number: 7039186
    Abstract: An encryption key generation circuit for generating at least one 128-bit round sub key used in at least one sub round for encryption of 128-bit plaintext, from an encryption key having 64×n bits (2?n?4; where n is an integer) includes a byte rotation circuit for performing byte rotation of rotating (8×n+1)-byte information by 1 byte; a 3-bit rotation circuit for performing 3-bit rotation of rotating bits in each byte of the (8×n+1) -byte information by 3 bits; and 16 adders for adding a 128-bit bias value to (8×n)-byte information from the byte lowest of the (8×n+1)-byte information processed with the byte rotation and the 3-bit rotation, so as to generate one of the at least one 128-bit round sub key in each sub round.
    Type: Grant
    Filed: October 31, 2001
    Date of Patent: May 2, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Masayuki Ezawa
  • Publication number: 20040189795
    Abstract: An image processing apparatus of the present invention is provided with (a) reduction calculation sections for reducing the number of a plurality of input image data, corresponding to a plurality of images that satisfy azimuth difference relations each other, in a lateral direction, (b) a three-dimensional processing section for combining the image data that have been reduced the number by the reduction calculation sections so as to prepare a three-dimensional image data; and (c) a display switching control section for switching and selecting which one of three-dimensional image data prepared by the three-dimensional processing section and two-dimensional image data prepared by using one of the plurality of input image data should be outputted from the image processing apparatus.
    Type: Application
    Filed: February 6, 2004
    Publication date: September 30, 2004
    Inventor: Masayuki Ezawa
  • Publication number: 20040141064
    Abstract: In a folding information terminal device capable of taking a three-dimensional image and including two planes which become opposite to each other when the folding information terminal device is folded; there is provided at least one image pickup section on one plane of the two planes, and at least one image pickup section on the other plane. On this account, the information terminal device becomes capable of taking and displaying a superior three-dimensional image than that taken by a conventional device.
    Type: Application
    Filed: January 12, 2004
    Publication date: July 22, 2004
    Inventor: Masayuki Ezawa
  • Publication number: 20020051535
    Abstract: An encryption key generation circuit for generating at least one 128-bit round sub key used in at least one sub round for encryption of 128-bit plaintext, from an encryption key having 64×n bits (2≦n≦4; where n is an integer) includes a byte rotation circuit for performing byte rotation of rotating (8×n+1)-byte information by 1 byte; a 3-bit rotation circuit for performing 3-bit rotation of rotating bits in each byte of the (8×n+1) -byte information by 3 bits; and 16 adders for adding a 128-bit bias value to (8×n)-byte information from the byte lowest of the (8×n+1)-byte information processed with the byte rotation and the 3-bit rotation, so as to generate one of the at least one 128-bit round sub key in each sub round.
    Type: Application
    Filed: October 31, 2001
    Publication date: May 2, 2002
    Inventor: Masayuki Ezawa
  • Patent number: 6067120
    Abstract: A video signal conversion device of the present includes a flicker reduction section including a plurality of line buffers for storing data in accordance with an address thereof. The flicker reduction section receives non-interlaced signals, converts the non-interlaced signals to interlaced signals and performs a flicker reduction process.
    Type: Grant
    Filed: August 26, 1998
    Date of Patent: May 23, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Koji Horikawa, Hideaki Kawamura, Masayuki Ezawa