Patents by Inventor Masayuki Fukumi

Masayuki Fukumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190367038
    Abstract: A driver monitoring device is provided with a driver monitoring camera that takes an image of a face of a driver, a detection unit that detects safety check action information related to a safety check action of the driver on the basis of a face image of the driver captured by the driver monitoring camera, and a determination unit that determines whether or not the driver is neglecting the safety check action on the basis of the safety check action information detected by the detection unit.
    Type: Application
    Filed: April 30, 2019
    Publication date: December 5, 2019
    Inventor: MASAYUKI FUKUMI
  • Patent number: 10332976
    Abstract: A nitride semiconductor device includes a second insulating film (22) covering at least a drain electrode (19) and a thermal stress reducer that reduces thermal stress in a place where thermal stress that is generated between the drain electrode (19) and the second insulating film (22) reaches its maximum at the time of a load short. The thermal stress reducer (19bf) is a drain field plate portion (19bf) formed by an extension of an upper part of the drain electrode (19) toward a source electrode (18).
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: June 25, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hisao Ichijoh, Masaru Kubo, Masayuki Fukumi, Norihisa Fujii
  • Publication number: 20180331190
    Abstract: A nitride semiconductor device includes a second insulating film (22) covering at least a drain electrode (19) and a thermal stress reducer that reduces thermal stress in a place where thermal stress that is generated between the drain electrode (19) and the second insulating film (22) reaches its maximum at the time of a load short. The thermal stress reducer (19bf) is a drain field plate portion (19bf) formed by an extension of an upper part of the drain electrode (19) toward a source electrode (18).
    Type: Application
    Filed: March 30, 2016
    Publication date: November 15, 2018
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: HISAO ICHIJOH, MASARU KUBO, MASAYUKI FUKUMI, NORIHISA FUJII
  • Publication number: 20170352753
    Abstract: A field-effect transistor includes: a nitride semiconductor layer that includes a heterojunction; a source electrode and a drain electrode that are disposed on the nitride semiconductor layer at an interval; a first gate electrode that is located between the source electrode and the drain electrode and performs a normally-on operation; and a second gate electrode that is located between the first gate electrode and the source electrode and performs a normally-off operation. The first gate electrode is disposed to surround the drain electrode in plan view. The second gate electrode is disposed to surround the source electrode in plan view.
    Type: Application
    Filed: August 24, 2015
    Publication date: December 7, 2017
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Tetsuzo NAGAHISA, Masayuki FUKUMI, Shinichi HANDA
  • Publication number: 20170345920
    Abstract: A field-effect transistor includes: a nitride semiconductor layer that includes a heterojunction; a source electrode and a drain electrode; a first gate electrode that is disposed to surround the drain electrode in a plan view and performs a normally-on operation; and a second gate electrode is disposed to surround the first gate electrode in a plan view and performs a normally-off operation. The first gate electrode and the second gate electrode include straight portions in which both an edge of the first gate electrode and an edge of the second gate electrode are substantially straight in the plan view and end portions formed by corner portions which are curved or bent in the plan view. An interval, a length, or a radius of curvature of one of the first gate electrode, the second gate electrode, and the source electrode is set such that concentration of an electric field at the end portion is alleviated.
    Type: Application
    Filed: August 21, 2015
    Publication date: November 30, 2017
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Tetsuzo NAGAHISA, Masayuki FUKUMI, Shinichi HANDA
  • Publication number: 20070120265
    Abstract: A semiconductor device comprises at least one first electrode 11b provided on the front surface of a semiconductor chip and electrically connected to at least one of electrodes that constitute a transistor, a second electrode 9 provided on the back surface of the semiconductor chip and electrically connected to one of the other electrodes, a via hole penetrating the semiconductor chip from the front surface to the back surface, and a through electrode 11a a part of which is exposed on the front surface of the semiconductor chip electrically connected to the second electrode 9 through the via hole.
    Type: Application
    Filed: November 22, 2006
    Publication date: May 31, 2007
    Inventors: Masayuki Fukumi, Alberto Adan
  • Patent number: 6812508
    Abstract: A semiconductor substrate device comprises a first semiconductor substrate including a concave-convex surface and a second semiconductor substrate having an insulating film on a surface thereof. The first semiconductor substrate and the second semiconductor substrate are brought together so that the surface of the first semiconductor substrate and the insulating film provided on the surface of the second semiconductor substrate contact each other to form a cavity in the semiconductor substrate device.
    Type: Grant
    Filed: November 27, 2001
    Date of Patent: November 2, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Masayuki Fukumi
  • Publication number: 20020063341
    Abstract: A semiconductor substrate device comprises a first semiconductor substrate including a concave-convex surface and a second semiconductor substrate having an insulating film on a surface thereof. The first semiconductor substrate and the second semiconductor substrate are brought together so that the surface of the first semiconductor substrate and the insulating film provided on the surface of the second semiconductor substrate contact each other to form a cavity in the semiconductor substrate device.
    Type: Application
    Filed: November 27, 2001
    Publication date: May 30, 2002
    Inventor: Masayuki Fukumi
  • Patent number: 6294399
    Abstract: A Si protruding portion is formed on a Si substrate by opportunely using the general film forming technique, photolithographic technique and etching technique. A second oxide film is formed to fill up a space between Si protruding portions, and the surface is flattened by the CMP method or the like. Then, the second oxide film is subjected to anisotropic etching to form a Si exposed portion at the top of the Si protruding portion. A Si thin line is made to grow in this Si exposed portion, and then a third oxide film for isolating the Si thin line from the Si substrate is formed through oxidation. A quantum thin line is thus formed at low cost without using any special technique of SOI or the like. Furthermore, the substrate surface is flattened, allowing the formation of a single electron device or a quantum effect device to be easy. The quantum thin line is isolated from the Si substrate by the third oxide film, completely confining the electron.
    Type: Grant
    Filed: January 27, 2000
    Date of Patent: September 25, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masayuki Fukumi, Yasumori Fukushima