Patents by Inventor Masayuki Furuhashi

Masayuki Furuhashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120009801
    Abstract: In a silicon carbide MOSFET, interface state generated at an interface between a silicon carbide layer and a gate insulating film cannot be reduced sufficiently, and mobility of a carrier is decreased. To solve this problem, a silicon carbide semiconductor device according to this invention includes a substrate introduction step of introducing a substrate, which includes a silicon carbide layer on which a gate insulating film is formed, in a furnace, and a heating step of heating the furnace having the substrate introduced therein while introducing nitrogen monoxide and nitrogen therein, wherein, in the heating step, nitrogen is reacted to nitride an interface between the gate insulating film and the silicon carbide layer.
    Type: Application
    Filed: March 10, 2010
    Publication date: January 12, 2012
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Toshikazu Tanioka, Masayuki Furuhashi, Masayuki Imaizumi
  • Patent number: 8035178
    Abstract: A plurality of pixel portions (12) are formed on a silicon substrate (11). A photoelectric converter portion (10) constituting each of the pixel portions (12) is electrically isolated by an element isolation portion (13) comprising an insulating film formed on the silicon substrate (11). The photoelectric converter portion (10) partitioned by the element isolation portion (13) is so formed that a crystal orientation of the sides in contact with the element isolation portion (13) corresponds to a <00-1> direction. This makes it possible to reduce dark current caused by stress in the vicinity of the interface of the element isolation portion (13) and maintain high sensitivity even if the pixel portions (12) are made smaller in size.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: October 11, 2011
    Assignee: Panasonic Corporation
    Inventors: Mitsuyoshi Mori, Yasuhiro Shimada, Takuma Katayama, Kenji Taniguchi, Masayuki Furuhashi
  • Publication number: 20100133592
    Abstract: A plurality of pixel portions (12) are formed on a silicon substrate (11). A photoelectric converter portion (10) constituting each of the pixel portions (12) is electrically isolated by an element isolation portion (13) comprising an insulating film formed on the silicon substrate (11). The photoelectric converter portion (10) partitioned by the element isolation portion (13) is so formed that a crystal orientation of the sides in contact with the element isolation portion (13) corresponds to a <00-1> direction. This makes it possible to reduce dark current caused by stress in the vicinity of the interface of the element isolation portion (13) and maintain high sensitivity even if the pixel portions (12) are made smaller in size.
    Type: Application
    Filed: June 24, 2008
    Publication date: June 3, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Mitsuyoshi Mori, Yasuhiro Shimada, Kenji Taniguchi, Masayuki Furuhashi
  • Publication number: 20090267256
    Abstract: An insert molding die, an insert molding apparatus and an insert molding method are disclosed, wherein a pair of dies 10a, 10b are arranged in a manner capable of clamping, from axis X side, an insert part 2 arranged along axis X to be insert molded. The dies 10a, 10b include first separated dies 10a1, 10b1, second separated dies 10a2, 10b2 and third separated dies 10a3, 10b3 adapted to perform the clamp operation independently of each other.
    Type: Application
    Filed: March 3, 2009
    Publication date: October 29, 2009
    Applicant: DENSO CORPORATION
    Inventors: Tsuyoshi Arai, Masayuki Furuhashi, Sayaka Okabe
  • Patent number: 7261854
    Abstract: An insert component (2) is located at a predetermined position between a pair of halves of a mold (1) in an open state while being held by a support (12) for holding the insert component (2) outside the mold. A tubular molten resin (4) is extruded through a die (3) between the pair of halves of the mold (1) to dispose the insert component (2) in the interior space (13) of the molten resin (4). By clamping the mold (1), the insert component (2) is covered with the tubular molten resin (4) in conformity with the contour thereof to result in an insert-mold product (20).
    Type: Grant
    Filed: February 18, 2004
    Date of Patent: August 28, 2007
    Assignee: DENSO Corporation
    Inventors: Tsuyoshi Arai, Masayuki Furuhashi
  • Publication number: 20070072381
    Abstract: The semiconductor device fabrication method comprises the step of forming gate electrode 20 on a semiconductor substrate 10 with a gate insulation film 18 formed therebetween; the step of implanting dopants in the semiconductor substrate 10 with the gate electrode 20 as the mask to form dopant diffused regions 28, 36; the step of forming a silicon oxide film 38 on the semiconductor substrate 10, covering the gate electrodes 20; anisotropically etching the silicon oxide film 38 to form sidewall spacers 42 including the silicon oxide film 38 on the side walls of the gate electrode 20. In the step of forming a silicon oxide film 38, the silicon oxide film 38 is formed by thermal CVD at a 500-580° C. film forming temperature, using bis (tertiary-butylamino) silane and oxygen as raw materials.
    Type: Application
    Filed: November 30, 2006
    Publication date: March 29, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Masayuki Furuhashi, Toshifumi Mori, Young Kim, Takayuki Ohba, Ryou Nakamura
  • Patent number: 7166516
    Abstract: The semiconductor device fabrication method comprises the step of forming gate electrode 20 on a semiconductor substrate 10 with a gate insulation film 18 formed therebetween; the step of implanting dopants in the semiconductor substrate 10 with the gate electrode 20 as the mask to form dopant diffused regions 28, 36; the step of forming a silicon oxide film 38 on the semiconductor substrate 10, covering the gate electrodes 20; anisotropically etching the silicon oxide film 38 to form sidewall spacers 42 including the silicon oxide film 38 on the side walls of the gate electrode 20. In the step of forming a silicon oxide film 38, the silicon oxide film 38 is formed by thermal CVD at a 500–580° C. film forming temperature, using bis(tertiary-butylamino)silane and oxygen as raw materials.
    Type: Grant
    Filed: October 30, 2003
    Date of Patent: January 23, 2007
    Assignee: Fujitsu Limited
    Inventors: Masayuki Furuhashi, Toshifumi Mori, Young Suk Kim, Takayuki Ohba, Ryou Nakamura
  • Publication number: 20050126308
    Abstract: A rotation detecting device includes a housing that has an open end, a bottom end and an inside wall, and a rotation sensing unit disposed inside the housing. The rotation sensing unit includes an IC unit and a shape adjusting member that covers the IC unit. The shape adjusting member has an outer periphery fitted to the inside wall of the housing to hold the IC unit tight in the housing.
    Type: Application
    Filed: October 28, 2004
    Publication date: June 16, 2005
    Inventors: Hiroyuki Tsuge, Masayuki Furuhashi
  • Publication number: 20050035489
    Abstract: An insert component (2) is located at a predetermined position between a pair of halves of a mold (1) in an open state while being held by a support (12) for holding the insert component (2) outside the mold. A tubular molten resin (4) is extruded through a die (3) between the pair of halves of the mold (1) to dispose the insert component (2) in the interior space (13) of the molten resin (4). By clamping the mold (1), the insert component (2) is covered with the tubular molten resin (4) in conformity with the contour thereof to result in an insert-mold product (20).
    Type: Application
    Filed: February 18, 2004
    Publication date: February 17, 2005
    Inventors: Tsuyoshi Arai, Masayuki Furuhashi
  • Patent number: 6800538
    Abstract: The method for fabricating a semiconductor device including a step of forming a gate insulation film on a semiconductor substrate 10, the method further comprises, before the step of forming the gate insulation film, the step of forming an insulation film 12, covering a first side (upper side) and a second side (underside) of the semiconductor substrate 10, the step of etching off the insulation film 12 on the first side of the semiconductor substrate 10, and the step of annealing the semiconductor substrate 10 with the insulation film 12 present on the second side of the semiconductor substrate 10.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: October 5, 2004
    Assignee: Fujitsu Limited
    Inventors: Masayuki Furuhashi, Mitsuaki Hori
  • Publication number: 20040132257
    Abstract: The semiconductor device fabrication method comprises the step of forming gate electrode 20 on a semiconductor substrate 10 with a gate insulation film 18 formed therebetween; the step of implanting dopants in the semiconductor substrate 10 with the gate electrode 20 as the mask to form dopant diffused regions 28, 36; the step of forming a silicon oxide film 38 on the semiconductor substrate 10, covering the gate electrodes 20; anisotropically etching the silicon oxide film 38 to form sidewall spacers 42 including the silicon oxide film 38 on the side walls of the gate electrode 20. In the step of forming a silicon oxide film 38, the silicon oxide film 38 is formed by thermal CVD at a 500-580° C. film forming temperature, using bis(tertiary-butylamino)silane and oxygen as raw materials.
    Type: Application
    Filed: October 30, 2003
    Publication date: July 8, 2004
    Inventors: Masayuki Furuhashi, Toshifumi Mori, Young Suk Kim, Takayuki Ohba, Ryou Nakamura
  • Publication number: 20040127068
    Abstract: The method for fabricating a semiconductor device including a step of forming a gate insulation film on a semiconductor substrate 10, the method further comprises, before the step of forming the gate insulation film, the step of forming an insulation film 12, covering a first side (upper side) and a second side (underside) of the semiconductor substrate 10, the step of etching off the insulation film 12 on the first side of the semiconductor substrate 10, and the step of annealing the semiconductor substrate 10 with the insulation film 12 present on the second side of the semiconductor substrate 10.
    Type: Application
    Filed: October 29, 2003
    Publication date: July 1, 2004
    Inventors: Masayuki Furuhashi, Mitsuaki Hori