Abstract: Provided is a constant voltage circuit having a stable output voltage. In a constant voltage circuit formed by connecting an enhancement type NMOS and a depression type NMOS in series, in order to enhance the back bias effect of the depression type NMOS, the impurity concentration is set to be high only in a P-type well region on which the depression type NMOS is arranged.

Abstract: A reference voltage generator includes a depletion NMOS transistor of a first conductivity type for causing a constant current to flow, and an enhancement NMOS transistor of the first conductivity type diode-connected to the depletion NMOS transistor to generate a reference voltage. A resistor surrounds the periphery of the depletion NMOS transistor and the periphery of the enhancement NMOS transistor. A diode is connected in series to a constant current source and provides a voltage that controls current flowing through the resistor when the environment temperature is lower than a preset temperature. The reference voltage generator can operate under a given preset temperature environment because a voltage consumed in the resistor becomes approximately constant in accordance with the voltage provided from the diode.

Abstract: A reference voltage generator has a first N type depletion MOS transistor configured to cause a constant current to flow, and a second N type depletion MOS transistor diode-connected to the first N type depletion MOS transistor and configured to generate a reference voltage based on the constant current. The first and second N type depletion MOS transistors have the same temperature coefficient of a threshold voltage. The first N type depletion MOS transistor has a buried channel into which arsenic impurities are diffused. The second N type depletion MOS transistor has a buried channel into which phosphorous impurities are diffused.

Abstract: Provided is a constant voltage circuit having a stable output voltage. In a constant voltage circuit formed by connecting an enhancement type NMOS and a depression type NMOS in series, in order to enhance the back bias effect of the depression type NMOS, the impurity concentration is set to be high only in a P-type well region on which the depression type NMOS is arranged.

Abstract: In the semiconductor device including the off transistor serving as an ESD protection element and an output element between a first external connection terminal and a second external connection terminal connected to a VSS, a seal ring wire is connected in parallel, by a connection wire, to a first internal wire extending from the second external connection terminal to the source of the off transistor, and a parasitic resistance of the first internal wire is smaller than a parasitic resistance of a second internal wire connecting the source of the off transistor and a source of the output element to each other.

Abstract: In the semiconductor device including the off transistor serving as an ESD protection element and an output element between a first external connection terminal and a second external connection terminal connected to a VSS, a seal ring wire is connected in parallel, by a connection wire, to a first internal wire extending from the second external connection terminal to the source of the off transistor, and a parasitic resistance of the first internal wire is smaller than a parasitic resistance of a second internal wire connecting the source of the off transistor and a source of the output element to each other.

Abstract: Provided is a semiconductor device formed with a trench portion for providing a concave portion in a gate width direction and with a gate electrode provided within and on a top surface of the trench portion via a gate insulating film. At least a part of a surface of each of the source region and the drain region is made lower than other parts of the surface by removing a thick oxide film formed in the vicinity of the gate electrode. Making lower the part of the surface of each of the source region and the drain region allows current flowing through a top surface of the concave portion of the gate electrode at high concentration to flow uniformly through the entire trench portion, which increase an effective gate width of the concave portion formed so as to have a varying depth in a gate width direction.

Abstract: A reference voltage generator has a depletion mode MOS transistor of a first conductivity type for supplying a constant current flow, and an enhancement mode MOS transistor of the first conductivity type having a diode connection to the depletion mode MOS transistor for generating a reference voltage based on a constant current supplied by the depletion mode MOS transistor. The enhancement mode MOS transistor has a mobility substantially equal to a mobility of the depletion mode MOS transistor such that the enhancement mode MOS transistor and the depletion mode MOS transistor have substantially equal temperature characteristics.

Abstract: Provided is a reference voltage circuit with improved temperature characteristics. A current based on a current flowing through a first depletion transistor whose gate and source are connected to each other is caused to flow through a third depletion transistor having the same threshold, to thereby generate a voltage between a gate and a source of the third depletion transistor. A current based on a current flowing through a second depletion transistor whose gate and source are connected to each other is caused to flow through a fourth depletion transistor having the same threshold, to thereby generate a voltage between a gate and a source of the fourth depletion transistor. A reference voltage is generated based on a difference voltage of the two voltages, to thereby obtain a reference voltage having less voltage fluctuations with respect to a temperature change.

Abstract: Provided is a reference voltage generator having flat temperature characteristics. The reference voltage generator includes a resistor (3) surrounding a periphery of a depletion MOS transistor (1) of a first conductivity type which is connected so as to function as a current source for causing a constant current to flow, and an enhancement MOS transistor (2) of the first conductivity type diode-connected thereto, and also includes a current source capable of being trimmed with high precision under a preset temperature environment and a diode connected in series to the current source. The reference voltage generator can operate under a given preset temperature environment because a voltage consumed in the resistor becomes approximately constant in accordance with a signal output from the diode.

Abstract: Provided is a reference voltage generator having flat temperature characteristics. The reference voltage generator includes a depletion MOS transistor (5) of a first conductivity type connected so as to function as a current source and configured to cause a constant current to flow, and a depletion MOS transistor (6) of the first conductivity type that is diode-connected to the depletion MOS transistor (5), has the same buried channel and temperature characteristics as those of the depletion MOS transistor (5), and is configured to generate a reference voltage based on the constant current. The depletion MOS transistor (5) and the depletion MOS transistor (6) have the same temperature characteristics, and hence temperature characteristics of an output from the reference voltage generator become flat.

Abstract: An oxide film is formed by STI in a silicon surface region in which a substrate potential heavily doped diffusion layer and a source heavily doped diffusion layer are to be provided later between trenches at predetermined intervals. The oxide film is removed after the trench is formed, to thereby form a region which is lower than a surrounding surface. Thus, in the vertical MOS transistor having a trench structure which includes a side spacer, a silicide on a gate electrode embedded in the trench and a silicide on the substrate potential heavily doped diffusion layer and the source heavily doped diffusion layer can be separated from each other.

Abstract: Provided is a semiconductor device formed with a trench portion for providing a concave portion in a gate width direction and with a gate electrode provided within and on a top surface of the trench portion via a gate insulating film. At least a part of a surface of each of the source region and the drain region is made lower than other parts of the surface by removing a thick oxide film formed in the vicinity of the gate electrode. Making lower the part of the surface of each of the source region and the drain region allows current flowing through a top surface of the concave portion of the gate electrode at high concentration to flow uniformly through the entire trench portion, which increase an effective gate width of the concave portion formed so as to have a varying depth in a gate width direction.

Abstract: Provided is a semiconductor device formed with a trench portion for providing a concave portion in a gate width direction and with a gate electrode provided within and on a top surface of the trench portion via a gate insulating film. At least a part of a surface of each of the source region and the drain region is made lower than other parts of the surface by removing a thick oxide film formed in the vicinity of the gate electrode. Making lower the part of the surface of each of the source region and the drain region allows current flowing through a top surface of the concave portion of the gate electrode at high concentration to flow uniformly through the entire trench portion, which increase an effective gate width of the concave portion formed so as to have a varying depth in a gate width direction.

Abstract: Provided is a constant voltage circuit having a stable output voltage. In a constant voltage circuit formed by connecting an enhancement type NMOS and a depression type NMOS in series, in order to enhance the back bias effect of the depression type NMOS, the impurity concentration is set to be high only in a P-type well region on which the depression type NMOS is arranged.

Abstract: Provided is a semiconductor device that includes a vertical MOS transistor having a trench structure capable of enhancing a driving performance of the vertical MOS transistor. A thick oxide film is formed next to a gate electrode led out of a trench of the vertical MOS transistor having the trench structure, and is removed to form a stepped portion which has a face lower than a surrounding plane and has slopes as well. This makes it possible to form a heavily doped diffusion layer right under the gate electrode through ion implantation for forming a heavily doped source diffusion layer, thereby solving a problem of no current flow in a part of a driver element and enhancing the driving performance of the vertical MOS transistor.

Abstract: In a method of manufacturing a semiconductor device, a buried layer is formed in a region of a semiconductor substrate and an epitaxial growth layer is formed on the buried layer and the semiconductor substrate. Trenches are formed in the epitaxial growth layer so as to be arranged side by side in a gate width direction of a transistor to be formed, and so that an entire bottom surface of each trench is entirely surrounded by and disposed in contact with the buried layer. A gate electrode is formed inside and on a top surface of each of the trenches and on a surface of the epitaxial growth layer adjacent to each of the trenches via a gate insulating film. A high concentration source diffusion layer is formed on one side of the gate electrode. A high concentration drain diffusion layer is formed on another side of the gate electrode.

Abstract: Provided is a semiconductor device formed with a trench portion for providing a concave portion having a continually varying depth in a gate width direction and with a gate electrode provided within the trench portion and on a top surface thereof via a gate insulating film. Before the formation of the gate electrode, an impurity is added to at least a part of the source region and the drain region by ion implantation from an inner wall of the trench portion, and then heat treatment is performed for diffusion and activation to form a diffusion region from the surface of the trench portion down to a bottom portion thereof. Current flowing through a top surface of the concave portion of the gate electrode at high concentration can flow uniformly through the entire trench portion.

Abstract: Provided is a semiconductor device that includes a vertical MOS transistor having a trench structure capable of enhancing a driving performance of the vertical MOS transistor. A thick oxide film is formed next to a gate electrode led out of a trench of the vertical MOS transistor having the trench structure, and is removed to form a stepped portion which has a face lower than a surrounding plane and has slopes as well. This makes it possible to form a heavily doped diffusion layer right under the gate electrode through ion implantation for forming a heavily doped source diffusion layer, thereby solving a problem of no current flow in a part of a driver element and enhancing the driving performance of the vertical MOS transistor.

Abstract: The semiconductor device includes a trench having a depth of a distance equal to or shorter than the L length of the transistor, and a buried layer is used in a bottom portion of the trench, whereby an effective channel length from each of a lower end of a high concentration source diffusion layer and a lower end of a high concentration drain diffusion layer to a bottom surface of the trench is made shorter than the shortest length L on a top surface of the trench. Accordingly, a current path is held on the bottom surface of the trench from a side surface thereof which contacts with the source or high concentration drain diffusion layer with a use of the buried layer, whereby the driving performance is enhanced. An effect of suppressing the decrease of the driving performance is obtained for the reduced gate length.