Abstract: The present invention embodies high-accuracy white point adjustment with a simple circuit configuration according to an efficient algorithm in a display system for full digital processing. More particularly, the present invention is directed to a digital video interface 13 for inputting a digital video signal outputted from a host system and a liquid-crystal display monitor 11 for applying color conversion to the digital video signal inputted by the digital video interface 13 without using a look-up table, in which an adjusted-value input logic for inputting adjusted values at predetermined points to achromatic colors between maximum- and minimum-gray-scale achromatic colors and a controller LSI 22 for computing a digital video signal inputted by the digital video interface 13 so as to converge chromaticity coordinates for achromatic colors and outputting a computed digital value in a pipeline manner are used.

Abstract: A method and apparatus for controlling tint in a digital color display system capable of efficiently performing tint control of displayed colors. The tint control method is executed according to the following: (1) when the maximum and the minimum among R, G, B are the maximum gray scale value and the minimum gray scale value respectively, a step of transforming the input color into a color of a different tint based on a use defined maximum transformation value and a transformation direction; (2) when the maximum and the minimum among R, G, B are Dmax and Dmin respectively, a step of transforming the input color into a color of a different tint based on a smaller transformation value and the same transformation direction; and (3) when all values R, G, B are equal, a step of not transforming the input color in accordance with any input set value.

Abstract: A synchronous signal separation circuit is disclosed which separates and fetches a synchronous signal from a video signal to which the synchronous signal has been added. The synchronous signal separation circuit includes an amplifier for amplifying a voltage of the video signal to output an amplified signal having an amplified voltage which is within a predetermined dynamic range. A voltage generator outputs a variable offset voltage to the amplifier for shifting a reference level of the amplified voltage to a predetermined level. A synchronous signal fetch means which, by comparing the amplified video signal with a threshold voltage in which the variable offset voltage has been adjusted based on the degree of amplification of the amplifier, fetches only the synchronous signal from the video signal.

Abstract: An arrangement for stabilizing a horizontal synchronization signal, serving as an input signal for a phase-locked loop (PLL) for generating a clock signal, by separating the horizontal synchronization signal from a composite synchronization signal including both horizontal and vertical synchronization signals. A horizontal synchronization gate signal is generated for outputting a pulse signal approximately in phase with the horizontal synchronization signal and having at least the pulse width of the horizontal synchronization signal in accordance with the composite synchronization signal and a clock pulse signal having a predetermined frequency. The horizontal synchronization signal is retrieved from the composite synchronization signal in accordance with a logical product when matching the polarity of the horizontal synchronization gate signal with the polarity of the composite synchronization signal.

Abstract: A display system for converting N bit signals, each representing 2.sup.N gray levels, to M bit signals representing 2.sup.M gray levels, where N is an integer larger than or equal to 2 and M is an integer satisfying N>M.gtoreq.1. Each of the N bit signals are separated into higher M bits and lower N-M bits. There are 2.sup.N-M tables, each of which stores a distinctive set of P.times.Q modification values satisfying P.times.Q.gtoreq.2.sup.N-M. One of the tables is selected using the N-M bits. Unequality between a first set of modification values and a second set of modification values of the selected table are detected. The first set of modification values and the second set of modification values are exchanged to generate a modified table of the selected table. The M bits of one N bit signal and each of the modification values of the selected table are added to generate a first set of P.times.Q M bit signals.