Abstract: In the present invention, there is provided an image processing apparatus including: a detecting section configured to detect a motion vector from an input image signal acting as the image signal for each of chronologically input pixels; a determining section configured to determine whether the input image signal is cleared; and an interpolating section configured such that if the input image signal is not found cleared, then the interpolating section interpolates and outputs an input image signal intermediate signal interposed at a predetermined point in time between the uncleared input image signal and a preceding input image signal that precedes the uncleared input signal, in accordance with the motion vector; and if the input image signal is found cleared, then the interpolating section allows the input image signal to be output unchanged as the input image signal intermediate signal.

Abstract: An image processing apparatus includes: a detecting unit configured to detect a motion vector from an input image signal acting as the image signal for each of chronologically input pixels; a determining unit configured to determine whether the input image signal in terms of a level meets a predetermined condition; and an interpolating unit configured such that if the input image signal is not found to meet the predetermined condition, then the interpolating unit interpolates and outputs an input image signal intermediate signal interposed at a predetermined point in time between the input image signal and a preceding input image signal that precedes the input image signal, in accordance with the motion vector, and if the input image signal is found to meet the predetermined condition, then the interpolating unit allows the input image signal to be output unchanged as the input image signal intermediate signal.

Abstract: A display apparatus including an image processing unit for performing a frame rate conversion process of converting a frame rate using an interpolating image generated based on a motion vector between adjacent frames with respect to a picture signal which is a collection of image signals of a plurality of frame units taken along a time-series; and a display unit for displaying a picture based on the picture signal of after the frame rate conversion process; wherein the image processing unit performs the frame rate conversion process using an image at least one part of which is the same as a frame immediately before as the interpolating image when an OSD superimposed picture signal having an OSD image signal superimposed on an input picture signal is input to the frame rate conversion section.

Abstract: In the present invention, there is provided an image processing apparatus including: a detecting section configured to detect a motion vector from an input image signal acting as the image signal for each of chronologically input pixels; a determining section configured to determine whether the input image signal is cleared; and an interpolating section configured such that if the input image signal is not found cleared, then the interpolating section interpolates and outputs an input image signal intermediate signal interposed at a predetermined point in time between the uncleared input image signal and a preceding input image signal that precedes the uncleared input signal, in accordance with the motion vector; and if the input image signal is found cleared, then the interpolating section allows the input image signal to be output unchanged as the input image signal intermediate signal.

Abstract: An image processing apparatus includes: a detecting unit configured to detect a motion vector from an input image signal acting as the image signal for each of chronologically input pixels; a determining unit configured to determine whether the input image signal in terms of a level meets a predetermined condition; and an interpolating unit configured such that if the input image signal is not found to meet the predetermined condition, then the interpolating unit interpolates and outputs an input image signal intermediate signal interposed at a predetermined point in time between the input image signal and a preceding input image signal that precedes the input image signal, in accordance with the motion vector, and if the input image signal is found to meet the predetermined condition, then the interpolating unit allows the input image signal to be output unchanged as the input image signal intermediate signal.

Abstract: An image displaying apparatus comprises a line memory from which each line period segment of a first video signal is read during a half line period to produce a first half line period video signal segment, first and second field memories, from each of which each of line period segments contained in each odd or even field period portion of a second video signal is read during a half line period to produce a second or third half line period video signal segment, a signal selector operative to extract alternately the first and second half line period video signal segments to form a first field period video signal portion or extract alternately the first and third half line period video signal segments to form a second field period video signal portion, a dual image display portion for displaying double window picture images in response to the first and second field period video signal portions, an overtaking detector for detecting an overtaking reading condition possibly caused in the first and second field memo

Abstract: An image displaying apparatus includes a line memory from which each line period segment of a first video signal is read during a half line period to produce a first half line period video signal segment, a frame memory from which each of line period segments contained in each frame period portion of a second video signal is read during a half line period, with a time reference set up in accordance with a synchronous signal contained in the first video signal, to produce a second half line period video signal segment, a signal selector operative to extract alternately the first and second half line period video signal segments to form a synthesized video signal for display, a dual image display portion for displaying images forming double window pictures in response to the synthesized video signal for display, a first timing signal generator for supplying the frame memory with a writing control signal, and a second timing signal generator for supplying the frame memory with a reading control signal, wherein t

Abstract: The nonlinear, deflection waveform used improve registration in a three picture tube projection television system is produced using interpolation of stored data setting points by first performing a reduced number of high-order interpolation calculations using the setting points and then performing low-order interpolation calculations either between two calculated high-order interpolated data points or between one of the calculated high-order interpolated data points and one of the setting points. This results in reducing the work load on the central processing unit in the registration system. In addition, a reduced bit-size requirement for the interpolation portion of the registration is obtained by storing registration data of a first bit size and then adding bits below the original LSB for the interpolation calculation prior to performing the digital to analog conversion.

Abstract: An additive video information inserting device includes a MUSE-NTSC converter, and an additive video information encoder for receiving an output video signal of the MUSE-NTSC converter and inserting into the video signal an additive video information indicating a frame mode for the video signal. The additive video information is so set as to correspond to a frame mode in a conversion operation of the MUSE-NTSC converter. The additive video information is inserted into a predetermined position in a vertical blanking period of the video signal.

Abstract: In a video additive information identifying device, one of plural video signal inputs each containing a video ID signal is inserted as video additive information on one line at a predetermined position within a vertical blanking period. The selected video signal input is subjected to a Y/C separation processing, and the video ID signal of the selected video signal is extracted from a Y-signal after separation to identify the content of the extracted video ID signal, that is, a frame mode. On the basis of the identification result, a display frame mode of a video display is controlled to be corrected.

Abstract: An infrared data transmission and reception system capable of avoiding adverse effects due to infrared external noises includes a data transmitting circuit and a data receiving circuit of which the former is so constructed as to add a signal-free region of a predetermined length or a trailer to the terminating end of each of the frames of a data bit pulse train and the latter is so constructed as to discriminate between transmitted data and external noise by detecting whether or not the region corresponding to the trailer is signal-free with respect to a detected output, whereby a proper encoding output is generated on the basis of the discrimination.

Abstract: In controlling an electronic apparatus, such as, a color television receiver, of the type having signal processing circuits which are individually adjustable in accordance with respective control signals provided by a microcomputer or central processing unit (CPU) in response to data corresponding to predetermined or standardized conditions of the adjustable circuits and which are stored in a non-volatile memory along with a secret code, operating keys selectively actuable to provide input data to the CPU for representing an externally applied code and, in a servicing mode of the receiver, for rewriting the data in the memory and thereby changing the standardized conditions of the adjustable circuits, and inner bus lines connecting the CPU to the adjustable circuits, the non-volatile memory and the operating keys; a standby power supply provides electric power to the CPU at a time when operating keys are actuated for inputting data representing an externally applied code to the CPU, a main power supply is tur

Abstract: Digitally controllable ICs or function blocks in an electronic apparatus are connected through control bus lines, and a switch device is provided for disconnecting one of the digitally controllable ICs or function blocks from the control bus so that the control bus is not disabled when that one IC is turned off or is not occupied when the IC is operating in its internal processing mode. Therefore, communication between the remaining ICs can be maintained through the control bus.

Abstract: A digital control system for electronic apparatus employs an internal bus system and includes at least one master controller and a plurality of operational circuits connected via control bus lines so that, during normal operation of the electronic apparatus, the master controller can carry out predetermined control operations relative to the respective circuit blocks. During testing and/or adjustment, an auxiliary master control circuit is connected to the control bus lines in order to control the operational circuitry in place of the master control circuit, while holding the master control in the slave mode.

Abstract: A control system for an electronic apparatus, such as a television receiver, having a control circuit with a control program in an internal memory sequentially communicates over an internal bus within predetermined intervals, such as within the vertical blanking interval of the television signal, with a plurality of controllable circuits in the television receiver, and the control circuit operates to select and communicate with a specific, selected one of the controllable circuits first, in each predetermined interval, with the remainder of the controllable circuits being subsequently communicated with in the remaining portion of the vertical blanking interval.

Abstract: A system for controlling electronic apparatus, such as a television receiver, which employs a control circuit having a control program in a read only memory to sequentially communicate over an internal system bus in a predetermined interval with a plurality of controllable, operational circuit blocks forming the electronic apparatus, in which the control circuit selects a specific circuit block for data transfer upon a request signal. In one embodiment, a request signal is transmitted prior to a vertical blanking interval in a television signal and in another embodiment, a dedicated line is provided from a selected controllable unit to the control unit, whereby the request signal can be transmitted at any time, irrespective of whether data is being transferred at such time.

Abstract: Digital data transfer in a digital television receiver between an internal central processing unit, or an external computer, and the video/audio processing circuitry by way of an internal bus is accomplished efficiently and without producing noise interference by using a high-frequency clock signal and a relatively low-frequency clock signal at different times. The high-frequency signal would normally produce visually perceptable noise, however, it is employed only during vertical blanking intervals, and the low-frequency clock signal, which would not produce visually perceptable noise, is used at all times other than the vertical blanking intervals, whereby noise interference that would be otherwise seen on the visual display of the television receiver is suppressed.

Abstract: First and second counters in a pulse width modulating circuit, whose respective outputs determine the trailing and leading edges of a pulse width modulated signal, count input clock pulses at a constant speed. The number of the pulses applied to the second counter during a cycle relative to the number of the pulses applied to the first counter is increased or decreased by one in response to a modulating pulse to change the counting phase of the second counter thereby changing the width of the pulse width modulated signal. Gates freeze the phases of the two counters at minimum and maximum pulse widths of the pulse width modulated signal to avoid abrupt jumps from minimum to maximum or vice versa.