Abstract: An object is to provide a control apparatus of a showcase in which appropriate illumination having a high presentation effect can be realized by an LED illumination apparatus having a high durability against turning ON/OFF and capable of securing a predetermined illumination intensity even under an environment at a low temperature. The control apparatus controls a plurality of showcases so that display chambers where commodities are displayed are illuminated with LED illumination apparatuses, and includes a person detecting sensor provided in a showcase disposed in such a position that the approaching of any person can first be detected among the plurality of arranged showcases, so that the approaching of the person is detected. When the person detecting sensor detects the approaching of the person, the illumination intensities of all the LED illumination apparatuses of the plurality of showcases are increased.

Abstract: An object is to provide a control apparatus of a showcase in which appropriate illumination having a high presentation effect can be realized by an LED illumination apparatus having a high durability against turning ON/OFF and capable of securing a predetermined illumination intensity even under an environment at a low temperature. The control apparatus controls a plurality of showcases so that display chambers where commodities are displayed are illuminated with LED illumination apparatuses, and includes a person detecting sensor provided in a showcase disposed in such a position that the approaching of any person can first be detected among the plurality of arranged showcases, so that the approaching of the person is detected. When the person detecting sensor detects the approaching of the person, the illumination intensities of all the LED illumination apparatuses of the plurality of showcases are increased.

Abstract: A computer system has a plurality of processing units (2-1,2-2,2-n) connected via one or more system buses (1-1,1-2). Each processing unit (2-1,2-2,2-n) has three or more processors (20-1,20-2,20-3) on a common support board (PL) and controlled by a common clock unit (1000). The three processors (20-1,20-2,20-3) perform the same operation and a fault in a processor (20-1,20-2, 20-3) is detected by comparison of the operations of the three processors (20-1,20-2,20-3). If one processor (20-1,20-2,20-3) fails, the operation can continue in the other two processors (20-1,20-2,20-3) of the processing unit (2-1,2-2,2-n), at least temporarily, before replacement of the entire processing unit (2-1,2-2, 2-n). Furthermore, the processing unit (2-1,2-2,2-n) may have a plurality of clocks (A,B) within the clock unit (1000), with a switching arrangement so that the processors (20-1,20-2,20-n) normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails.

Abstract: A computer system has a plurality of processing units connected via one or more system buses. Each processing unit has three or more processors on a common support board (PL) and controlled by a common clock unit. The three processors perform the same operation and a fault in a processor is detected by comparison of the operations of the three processors. If one processor fails, the operation can continue in the other two processors of the processing unit, at least temporarily, before replacement of the entire processing unit. Furthermore, the processing unit may have a plurality of clocks (A,B) within the clock unit, with a switching arrangement so that the processors normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails. Switching between the main and auxiliary clock (A,B) involves comparison of the pulse duration from the clocks (A,B).

Abstract: An information processing system capable of performance measurement by the use of a small amount of mounted hardware. The information processing system having central processors installed therein comprises a control circuit, and a performance measurement validation register for specifying whether a performance measurement function is valid or invalid. In a case where the validity of the measurement function has been specified by the register, the control circuit operates one loop in a duplex configuration as a performance measurement facility. At this time, counter #1-counter #3 are used as counters for totalizing performance information. On the other hand, in a case where the invalidity of the measurement function has been specified, both loops in the duplex configuration are operated as the central processors. At this time, the counter #1-the counter #3 are used as timer counters for controlling buses.

Abstract: A logical cache memory has a logical tag and a physical tag as address tags for comparison, and status information representing their status. Data status and block status are registered at the same entry position. When access is made using a logical address, access is made to the logical tag to detect the existence of data, and when access is made using a physical address, access is made to the physical tag using an offset portion which does not depend on address conversion, to detect the existence of data.

Abstract: A high-speed information processing in the information processing unit having a multiplexed bus is provided. A unit having a bus grant is stored in the next lowest priority unit memory circuits, and in the next bus arbitration cycle, bus arbitration is carried out by setting the lowest priority to the unit stored in the next lowest priority unit memory circuits. When a fault occurs in one of a plurality of buses and then the faulty bus recovered a normal operation status, the bus status supervising circuits output has fault recovery detecting signals and match the memory contents of the next lowest priority unit memory circuits together. With the above arrangement, an average bus waiting time can be minimized and the bus waiting time can be limited.

Abstract: A method and apparatus for controlling a dual bus system, capable of realizing high speed and continuous operation even if one of the buses of the dual bus system fails. The method and apparatus has a dual bus system, a plurality of electronic circuits connected to both buses of the dual bus system, and bus controller for providing a bus use allowance signal to one of the plurality of electronic circuits, the one electronic circuit being selected in accordance with bus occupation request signals issued from the plurality of electronic circuits requesting data transfer. If the bus occupation request signals for both buses of the dual bus system originates from the one selected electronic circuit and the outputs of the arbiters coincide, the bus use allowance signal is provided to the one selected electronic circuit for the allowance of occupying both buses of the dual bus system. A completion of data transfer at the dual bus system is determined when data transfer is completed at both buses.

Abstract: An interruption signal from a common input/output device is coupled to all processors through a common bus, and each processor issues to the common bus its own interruption receipt acceptance or negation state and the respective processors watch and decide individually interruption receipt acceptance or negation states on the common bus of the individual processors. Only one of processors which are ready to accept the receipt of interruption is allowed to accept the receipt of an interruption signal from the common input/output device in accordance with a predetermined priority.

Abstract: The present application invention relates to a method for restarting execution of an instruction interrupted due to a page fault. When a page fault occurs during an execution of an instruction, the pertinent page is loaded from an external storage into the main memory and then the access which has caused the page fault is executed again. After N steps of the microprogram that has executed the page fault access, the page fault exception processing is initiated and at the save/restore operation of the content of the microprogram counter, the content of the microprogram is decremented by N, thereby restarting the execution of the instruction beginning from the step of the microprogram which has achieved the page fault access.

Abstract: Method and apparatus for controlling interruption of a processor. When an external interrupt request having a higher priority level than a current program level is detected in the course of the execution of an instruction, the processing is interrupted and an interexecution interruption is issued. The program level is fixed in this interruption so that the interrupt request is processed as a normal interrupt request at an interruption destination, and the processing is resumed from the interrupted point at a second return instruction after the interrupt processing.