Patents by Inventor Masayuki Yojima

Masayuki Yojima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6133744
    Abstract: The present invention provides a semiconductor wafer tester including a substrate, at least one chip mounted on an upper surface of the substrate, the chip having function as a tester, the chip being electrically connected to a contact formed on a lower surface of the substrate through an internal wiring formed in the substrate, and a contact film having at least one first bump formed on an upper surface thereof and at least one second bump formed on a lower surface thereof, the first bump being electrically connected to the second bump through an internal wiring formed throughout the contact film, the contact film being to be disposed to be sandwiched between the substrate and a semiconductor wafer to be tested so that the first bump is in electrical contact with the contact of the substrate and the second bump is in electrical contact with the semiconductor wafer.
    Type: Grant
    Filed: April 25, 1996
    Date of Patent: October 17, 2000
    Assignee: NEC Corporation
    Inventors: Masayuki Yojima, Tohru Tsujide, Kazuo Nakaizumi
  • Patent number: 5392110
    Abstract: In a signal processing circuit, a height arithmetic circuit obtains a measured value of a height of an object by using the principle of triangulation from a second light receiving signal which is transmitted from a second photodetector of position detecting type thereto. An error arithmetic circuit acquires a measurement error by using the principle of triangulation from a first light receiving signal which is transmitted from a first photodetector of position detecting type thereto. A correction circuit calculates a correct height of the object by subtracting an output signal of the error arithmetic circuit from an output signal of the height arithmetic circuit.
    Type: Grant
    Filed: April 16, 1993
    Date of Patent: February 21, 1995
    Assignee: NEC Corporation
    Inventors: Masayuki Yojima, Masao Kinoshita