Patents by Inventor Mase Taub
Mase Taub has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11024380Abstract: Nonvolatile memory (e.g. phase change memory) devices, systems, and methods that minimize energy expenditure and wear while providing greatly improved error rate with respect to marginal bits are disclosed and described.Type: GrantFiled: November 15, 2019Date of Patent: June 1, 2021Assignee: Intel CorporationInventors: Daniel Chu, Kiran Pangal, Mase Taub, Sandeep Guliani, Raymond Zeng
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Publication number: 20200160908Abstract: Nonvolatile memory (e.g. phase change memory) devices, systems, and methods that minimize energy expenditure and wear while providing greatly improved error rate with respect to marginal bits are disclosed and described.Type: ApplicationFiled: November 15, 2019Publication date: May 21, 2020Inventors: Daniel Chu, Kiran Pangal, Mase Taub, Sandeep Guliani, Raymond Zeng
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Patent number: 10482960Abstract: Nonvolatile memory (e.g. phase change memory) devices, systems, and methods of programming the nonvolatile memory including sensing of a snapback current using a set demarcation voltage for set bit mapped cells and a reset demarcation voltage for reset bit mapped cells before selective writes.Type: GrantFiled: February 17, 2016Date of Patent: November 19, 2019Assignee: Intel CorporationInventors: Daniel Chu, Kiran Pangal, Mase Taub, Sandeep Guliani, Raymond Zeng
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Patent number: 10438659Abstract: In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback circuitry to apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.Type: GrantFiled: July 17, 2018Date of Patent: October 8, 2019Assignee: Intel CorporationInventors: Balaji Srinivasan, Daniel Chu, Lark-Hoon Leem, John Gorman, Mase Taub, Sandeep Guliani, Kiran Pangal
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Publication number: 20190013071Abstract: In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback circuitry to apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.Type: ApplicationFiled: July 17, 2018Publication date: January 10, 2019Applicant: Intel CorporationInventors: Balaji Srinivasan, Daniel Chu, Lark-Hoon Leem, John Gorman, Mase Taub, Sandeep Guliani, Kiran Pangal
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Patent number: 10032508Abstract: In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback circuitry to apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.Type: GrantFiled: December 30, 2016Date of Patent: July 24, 2018Assignee: Intel CorporationInventors: Balaji Srinivasan, Daniel Chu, Lark-Hoon Leem, John Gorman, Mase Taub, Sandeep Guliani, Kiran Pangal
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Publication number: 20180190353Abstract: In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback circuitry to apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.Type: ApplicationFiled: December 30, 2016Publication date: July 5, 2018Applicant: Intel CorporationInventors: Balaji Srinivasan, Daniel Chu, Lark-Hoon Leem, John Gorman, Mase Taub, Sandeep Guliani, Kiran Pangal
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Publication number: 20170236580Abstract: Nonvolatile memory (e.g. phase change memory) devices, systems, and methods of programming the nonvolatile memory including dual demarcation voltage sensing before writes.Type: ApplicationFiled: February 17, 2016Publication date: August 17, 2017Applicant: Intel CorporationInventors: Daniel Chu, Kiran Pangal, Mase Taub, Sandeep Guliani, Raymond Zeng
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Patent number: 7382591Abstract: A double cascode protected switchable voltage source may be used to selectively provide positive or negative voltage sources, for example, to a flash memory. The positive supply may be connected through a PMOS pass device to a first cascode protection device. A negative supply may be connected through an NMOS pass device and an NMOS cascode protection device to an output. The circuits may be designed so that exceeding snapback limits and gate aided drain breakdown are less likely.Type: GrantFiled: May 20, 2005Date of Patent: June 3, 2008Assignee: Intel CorporationInventors: Bi Han, Daniel Chu, Mase Taub
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Publication number: 20060267414Abstract: A double cascode protected switchable voltage source may be used to selectively provide positive or negative voltage sources, for example, to a flash memory. The positive supply may be connected through a PMOS pass device to a first cascode protection device. A negative supply may be connected through an NMOS pass device and an NMOS cascode protection device to an output. The circuits may be designed so that exceeding snapback limits and gate aided drain breakdown are less likely.Type: ApplicationFiled: May 20, 2005Publication date: November 30, 2006Inventors: Bi Han, Daniel Chu, Mase Taub
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Publication number: 20060001479Abstract: Methods and apparatuses associated with providing a bias voltage for an n-type and a p-type device. A high voltage may be received and used to derive a bias voltage that would reduce a risk of gate-aided breakdown of the drain-to-substrate channel-side pn-junction in an n-type device. The high voltage may be used to derive a bias voltage that would reduce the risk of gate-aided breakdown of the drain-to-substrate channel-side pn-junction in a p-type device.Type: ApplicationFiled: June 30, 2004Publication date: January 5, 2006Inventors: Gerald Barkley, Mase Taub
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Publication number: 20030208699Abstract: A method and apparatus to provide a low voltage reference generation. The apparatus includes a reference voltage generator to receive a first input voltage signal and output a reference voltage signal. A voltage level detector electrically coupled to the reference voltage generator to receive the reference voltage signal and also receive a second input voltage signal. The voltage level detector compares the second input voltage signal to the reference voltage signal for generating an output based on the compared signals.Type: ApplicationFiled: May 23, 2003Publication date: November 6, 2003Inventors: Mase Taub, Rajesh Sundaram, Kerry Tedrow
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Patent number: 6628108Abstract: A method and apparatus to provide a low voltage reference generation. The apparatus includes a reference voltage generator to receive a first input voltage signal and output a reference voltage signal. A voltage level detector electrically coupled to the reference voltage generator to receive the reference voltage signal and also receive a second input voltage signal. The voltage level detector compares the second input voltage signal to the reference voltage signal for generating an output based on the compared signals.Type: GrantFiled: December 22, 2000Date of Patent: September 30, 2003Assignee: Intel CorporationInventors: Mase Taub, Rajesh Sundaram, Kerry Tedrow
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Patent number: 6522180Abstract: An apparatus to provide a novel bi-voltage level switching. The apparatus includes a first level shifting buffer coupled to a voltage supply, an input, and a first transistor. The first transistor coupled to the voltage supply and an output. A second level shifting buffer coupled to the voltage supply, the input and second transistor. The second transistor coupled to the output and a voltage source.Type: GrantFiled: December 21, 2000Date of Patent: February 18, 2003Assignee: Intel CorporationInventors: Raymond Zeng, Bo Li, Mase Taub
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Patent number: 6255896Abstract: The present invention provides a method, apparatus, and system for rapid transition of a charge pump circuit from a low power state to a high power state. The charge pump circuit has at least one pump stage. The at least one pump stage includes at least a first capacitor coupled to a gate of a first switching transistor forming a boot node and at least a second capacitor coupled to an output node of the at least one pump stage. It is determined whether the charge pump circuit is in the low power state or the high power state. If the charge pump circuit is in the low power state, a first predetermined voltage and a second predetermined voltage that are different than the ground voltage level are applied to the boot node and the output node, respectively. If the charge pump circuit is in the high power state, the first predetermined voltage and the second predetermined voltage are removed from the boot node and the output node, respectively.Type: GrantFiled: September 27, 1999Date of Patent: July 3, 2001Assignee: Intel CorporationInventors: Bo Li, Marc E. Landgraf, Mase Taub, Sandeep K. Guliani
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Patent number: 5880622Abstract: A method and apparatus for controlling a charge pump. A detection circuit is used to assert a detect signal when a power supply voltage exceeds a first threshold voltage and deassert the detect signal in response to a trigger. The detect signal is used to force a charge pump to operate in a mode that drives the capacitive node at its output to the target voltage with reduced latency. This is particularly useful for a device which may operate the charge pump in a reduced power mode which is designed to maintain the node voltage at reduced power rather than drive it to the degree necessary for reduced latency during power up.Type: GrantFiled: December 17, 1996Date of Patent: March 9, 1999Assignee: Intel CorporationInventors: Jeff Evertt, Jahanshir J. Javanifard, Mase Taub
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Patent number: 5339272Abstract: A precision voltage reference circuit which includes a pair of similar flash EEPROM memory cells, each of the pair of similar flash EEPROM memory cells having a different charge on its floating gate; circuitry for connecting each of said cells in a pair of parallel circuits in which equal current values are generated in an equilibrium condition; apparatus for sensing a voltage in each of said pair of parallel circuits to provide an output voltage which may be used as a reference value when the currents are in equilibrium; and apparatus for sensing variations in the output voltage to vary the current through the flash EEPROM memory cells to bring the currents into equilibrium when the reference voltage varies from the voltage provided at equilibrium.Type: GrantFiled: December 21, 1992Date of Patent: August 16, 1994Assignee: Intel CorporationInventors: Kerry Tedrow, Mase Taub, Neal Mielke