Abstract: A method detects border tiles or border pixels of a primitive corresponding to an object to be displayed on a display screen. The detecting includes: calculating the number of border tiles or pixels covered by an edge of the primitive; identifying a plurality of vertices that divide the edge in a plurality of segments of equal length; calculating coordinates of the vertices; and associating a tile or pixel with the coordinates of each vertex. The number of vertices for the edge is greater than or equal to the number of border tiles or pixels.

Abstract: A digital video image is compressed by determining for a group of adjacent pixels the global error values that result from the available combinations of truncation and integration of data strings associated with the group of pixels. A combination of truncation and integration that produces a minimum global error value is identified and used to control compression of the individual strings of data associated with the group of pixels.

Abstract: A primitive binning method includes detecting border tiles of a primitive defined by at least three vertexes. The detecting includes: defining a left edge and a right edge of the primitive compared to a direction of exploring tiles; calculating a slope sign for the left edge using an edge equation for the left edge; calculating a slope sign for the right edge using an edge equation for the right edge; and checking if a tile is crossed by one of the edges by evaluating an edge equation of a single corner of a tile. The corner is selected according to the one of the edges being a left or a right edge and according to the slope sign of the one of the edges.

Abstract: An antialiasing method includes: providing a first fragment; computing a first coverage area representing a portion of the first fragment covered by a first primitive; providing a second fragment juxtaposed to the first fragment and at least partially covered by a second primitive; processing the first coverage area to obtain a corrected coverage area indicative of a visible first fragment portion resulting from the juxtaposition of the fragments; and applying an antialiasing procedure based on the corrected coverage area.

Abstract: A method for texture compressing images having a plurality of color components (R, G, B) includes defining color representatives for use in encoding by defining groups of colors for each color component (R,G,B), and selecting a representative median color for the group. Each group ideally includes 3 to 15 increasing colors. The method includes computing, for each group, an error between each member of the group and the representative median color of the group. Typically, the error is computed as the sum of the absolute differences (SAD) between each member of the group and the representative median color of the group.

Abstract: A graphic system includes a pipelined graphic engine for generating image frames for display. The pipelined graphic engine includes a geometric processing stage for performing motion extraction, and a rendering stage for generating full image frames at a first frame rate for display at a second frame rate. The second frame rate is higher than the first frame rate. A motion encoder stage receives motion information from the geometric processing stage, and produces an interpolated frame signal representative of interpolated frames. A motion compensation stage receives the interpolated frame signal from the motion encoder stage, and the full image frames from the rendering stage for generating the interpolated frames. A preferred application is in graphic systems that operate in association with smart displays through a wireless connection, such as in mobile phones.

Abstract: A method for texture compressing images having a plurality of color components (R, G, B), includes decomposing the images in sub-blocks each including only one color component. At least one first predictor is defined for each sub-block and a respective set of prediction differences is computed for each sub-block. Then the prediction differences for each sub-block are sorted, and a look-up prediction differences palette is set up by defining a look-up prediction error palette. A predetermined code is associated with each column of the error palette.

Abstract: A geometric processing stage for a pipelined engine for processing video signals and generating processed video signal in space coordinates (S) adapted for display on a screen. The geometric processing stage includes: a model view module for generating projection coordinates of primitives of the video signals in a view space, said primitives including visible and non-visible primitives, a back face culling module arranged downstream of the model view module for at least partially eliminating the non visible primitives, a projection transform module for transforming the coordinates of the video signals from view space coordinates into normalized projection coordinates (P), and a perspective divide module for transforming the coordinates of the video signals from normalized projection (P) coordinates into screen space coordinates (S). The back face culling module is arranged downstream the projection transform module and operates on normalized projection (P) coordinates of said primitives.

Abstract: A built-in self-test circuit adapted to be embedded in an integrated circuit for testing the integrated circuit, including in particular a collection of addressable elements, for example a semiconductor memory. The BIST circuit comprises a general-purpose data processor programmable for executing a test program for testing the integrated circuit. The BIST circuit comprises an accelerator circuit cooperating with the general-purpose data processor for autonomously conducting operations on the integrated circuit according to the test program. The accelerator circuit comprises configuration means adapted to be loaded with configuration parameters for adapting the accelerator circuit to the specific type of integrated circuit and the specific type of test program.

Abstract: A system renders a primitive of an image to be displayed, for instance in a mobile 3D graphic pipeline, the primitive including a set of pixels. The system locates the pixels in the area of the primitive, generates, for each pixel located in the area, a set of associated sub-pixels, borrows a set of sub-pixels from neighboring pixels, subjects the set of associated sub-pixels and the borrowed set of pixels to adaptive filtering to create an adaptively filtered set of sub-pixels, and further filters the adaptively filtered set of sub-pixels to compute a final pixel for display. Preferably, the set of associated sub-pixels fulfils at least one of the following: the set includes two associated sub-pixels and the set includes associated sub-pixels placed on triangle edges.

Abstract: Described herein is a method for compressing a sequence of repetitive data, which uses in combination one or more words with a format for non-compressible data and one or more words with a format for compressible data, in which a word with a format for non-compressible data is made up of a set of bits, in which the most significant bit is set at the logic value “1” and the remaining bits are the bits of a non-compressible datum to be encoded, whilst a word with a format for compressible data is made up of a set of bits, in which the most significant bit is set at a the logic value “0”, the next five most significant bits indicate the total number of subsequent words which encode the sequence of repetitive data, and the remaining eleven bits indicate the number of times that the words indicated by the preceding five most significant bits are repeated.

Abstract: A dither matrix is applied to a high-resolution image to compare the value of each of the pixels that compose it with a threshold value of the matrix and to obtain an output value of the matrix (Dither matrix value) from each comparison. To each pixel value of the image there is applied an algorithm involving simple but displacement operation, namely shifts to the left and shifts to the right. The pixel values of a low-resolution image are output from the applied algorithm.

Abstract: A geometric processing stage for a pipelined engine for processing video signals and generating processed video signal in space coordinates (S) adapted for display on a screen. The geometric processing stage includes: a model view module for generating projection coordinates of primitives of the video signals in a view space, said primitives including visible and non-visible primitives, a back face culling module arranged downstream of the model view module for at least partially eliminating the non visible primitives, a projection transform module for transforming the coordinates of the video signals from view space coordinates into normalized projection coordinates (P), and a perspective divide module for transforming the coordinates of the video signals from normalized projection (P) coordinates into screen space coordinates (S). The back face culling module is arranged downstream the projection transform module and operates on normalized projection (P) coordinates of said primitives.

Abstract: A digital video image is compressed by determining for a group of adjacent pixels the global error values that result from the available combinations of truncation and integration of data strings associated with the group of pixels. A combination of truncation and integration that produces a minimum global error value is identified and used to control compression of the individual strings of data associated with the group of pixels.

Abstract: A graphic system includes a pipelined graphic engine for generating image frames for display. The pipelined graphic engine includes a geometric processing stage for performing motion extraction, and a rendering stage for generating full image frames at a first frame rate for display at a second frame rate. The second frame rate is higher than the first frame rate. A motion encoder stage receives motion information from the geometric processing stage, and produces an interpolated frame signal representative of interpolated frames. A motion compensation stage receives the interpolated frame signal from the motion encoder stage, and the full image frames from the rendering stage for generating the interpolated frames. A preferred application is in graphic systems that operate in association with smart displays through a wireless connection, such as in mobile phones.

Abstract: A method for texture compressing images having a plurality of color components (R, G, B), includes decomposing the images in sub-blocks each including only one color component. At least one first predictor is defined for each sub-block and a respective set of prediction differences is computed for each sub-block. Then the prediction differences for each sub-block are sorted, and a look-up prediction differences palette is set up by defining a look-up prediction error palette. A predetermined code is associated with each column of the error palette.

Abstract: A method for texture compressing images having a plurality of color components (R, G, B) includes defining color representatives for use in encoding by defining groups of colors for each color component (R,G,B), and selecting a representative median color for the group. Each group ideally includes 3 to 15 increasing colors. The method includes computing, for each group, an error between each member of the group and the representative median color of the group. Typically, the error is computed as the sum of the absolute differences (SAD) between each member of the group and the representative median color of the group.

Abstract: A built-in self-test circuit adapted to be embedded in an integrated circuit for testing the integrated circuit, including in particular a collection of addressable elements, for example a semiconductor memory. The BIST circuit comprises a general-purpose data processor programmable for executing a test program for testing the integrated circuit. The BIST circuit comprises an accelerator circuit cooperating with the general-purpose data processor for autonomously conducting operations on the integrated circuit according to the test program. The accelerator circuit comprises configuration means adapted to be loaded with configuration parameters for adapting the accelerator circuit to the specific type of integrated circuit and the specific type of test program.