Patents by Inventor Massimiliano Frulio
Massimiliano Frulio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11328752Abstract: A self-timed sensing architecture for reading a selected cell in an array of non-volatile cells is disclosed. The sensing circuitry generates a signal when a stable sensing value has been obtained from the selected cell, where the stable sensing value indicates the value stored in the selected cell. The signal indicates the end of the sensing operation, causing the stable sensing value to be output as the result of the read operation.Type: GrantFiled: November 11, 2020Date of Patent: May 10, 2022Assignee: Silicon Storage Technology, Inc.Inventor: Massimiliano Frulio
-
Publication number: 20210366522Abstract: A self-timed sensing architecture for reading a selected cell in an array of non-volatile cells is disclosed. The sensing circuitry generates a signal when a stable sensing value has been obtained from the selected cell, where the stable sensing value indicates the value stored in the selected cell. The signal indicates the end of the sensing operation, causing the stable sensing value to be output as the result of the read operation.Type: ApplicationFiled: November 11, 2020Publication date: November 25, 2021Inventor: Massimiliano Frulio
-
Patent number: 9489990Abstract: In an embodiment, a method of programming non-volatile memory (NVM) comprises: determining, by control logic of an NVM system, a number of unsuccessful attempts to program NVM cells; responsive to the determining, dividing the NVM cells into at least a first group and a second group; programming the first group during a first programming cycle; and programming the second group during a second programming cycle, wherein the first programming cycle and second programming cycle are different.Type: GrantFiled: November 17, 2015Date of Patent: November 8, 2016Assignee: Atmel CorporationInventor: Massimiliano Frulio
-
Patent number: 7684245Abstract: In an embodiment, a non-volatile memory array wherein narrow word lines, as small as the minimum feature size width F, in separate strings, are extended outwardly from a non-volatile memory array and joined by wider connector segments. The joined word lines provide new opportunities. First, metal straps that can be formed to overlie the word lines can be joined by metal connector segments to the word lines. The connector segments can serve as an interface between the polysilicon word lines and the metal straps. Two adjacent word lines in the same string share a single metal strap using these segments thereby reducing the overall number of segments and contacts in the array. Increased width of the polysilicon joinder segments joining word lines in different strings, provides the opportunity for widening the connection beyond the minimum feature size so that contact may be readily made between the metal straps and the polysilicon word lines. Second, the joined word lines require fewer row decoder circuits.Type: GrantFiled: October 30, 2007Date of Patent: March 23, 2010Assignee: Atmel CorporationInventors: Steve Schumann, Massimiliano Frulio, Simone Bartoli, Lorenzo Bedarida, Edward Shue-Ching Hui
-
Patent number: 7589572Abstract: Apparatus, systems, and methods are disclosed that operate to trigger a reference voltage generator from a supply voltage detector, compare an output voltage level from the reference voltage generator with a supply voltage, and to generate an enable signal when the supply voltage is greater than the output voltage level. Additional apparatus, systems, and methods are disclosed.Type: GrantFiled: December 15, 2006Date of Patent: September 15, 2009Assignee: Atmel CorporationInventors: Massimiliano Frulio, Stefano Surico, Andrea Bettini, Monica Marziani
-
Patent number: 7579902Abstract: A charge pump circuit for generating a plurality of voltages in excess of a supply voltage includes a first group of cascaded charge-pump stages, the input of a first charge pump stage in the first group being driven from the supply voltage. A first output stage has an input driven from the output of a last charge pump stage of the first group and an output coupled to a first voltage node. A second group of cascaded charge-pump stages is provided, the input of the first charge pump stage of the second group being driven from the output of the last charge pump stage of the first group. A second output stage has an input driven from the output of the last charge pump stage in the second group and an output coupled to a second voltage node.Type: GrantFiled: December 11, 2006Date of Patent: August 25, 2009Assignee: Atmel CorporationInventors: Massimiliano Frulio, Stefano Sivero, Marco Passerini, Fabio Tassan Caser
-
Publication number: 20090109754Abstract: In an embodiment, a non-volatile memory array wherein narrow word lines, as small as the minimum feature size width F, in separate strings, are extended outwardly from a non-volatile memory array and joined by wider connector segments. The joined word lines provide new opportunities. First, metal straps that can be formed to overlie the word lines can be joined by metal connector segments to the word lines. The connector segments can serve as an interface between the polysilicon word lines and the metal straps. Two adjacent word lines in the same string share a single metal strap using these segments thereby reducing the overall number of segments and contacts in the array. Increased width of the polysilicon joinder segments joining word lines in different strings, provides the opportunity for widening the connection beyond the minimum feature size so that contact may be readily made between the metal straps and the polysilicon word lines. Second, the joined word lines require fewer row decoder circuits.Type: ApplicationFiled: October 30, 2007Publication date: April 30, 2009Applicant: ATMEL CORPORATIONInventors: Steve Schumann, Massimiliano Frulio, Simone Bartoli, Lorenzo Bedarida, Edward Shue Ching Hui
-
Patent number: 7525856Abstract: A serial-interface flash memory device includes a data/address I/O pin and a clock input pin. A bidirectional buffer is coupled to the data/address I/O pin. A serial interface logic block including data direction control is coupled to the clock pin, the bidirectional buffer, to internal control logic, and to read-voltage and modify-voltage generators. A first switch is coupled to the read-voltage generator and the clock buffer and a second switch is coupled to the modify-voltage generator and the clock buffer, the first and second switches each having a control input. Memory drivers are coupled to the read-voltage generator and the modify-voltage generator through the first and second switches. First and second registers coupled between the serial interface logic and the first and second switches. A memory array is coupled to the memory drivers and read amplifiers and program buffers are coupled between the serial interface logic and the memory drivers.Type: GrantFiled: April 4, 2007Date of Patent: April 28, 2009Assignee: Atmel CorporationInventors: Stefano Surico, Marco Passerini, Massimiliano Frulio, Alex Pojer
-
Patent number: 7522463Abstract: A sense amplifier circuit for reading the state of memory cells. In one aspect of the invention, the sense amplifier circuit includes a first stage receiving a cell current derived from the memory cell and a reference current derived from a reference cell, and a second stage receiving the cell current and the reference current. A comparator, coupled to the first stage and the second stage, provides an output indicative of the state of the memory cell based on a difference of the voltages provided by the first stage and the second stage, where the state indicated by the comparator is substantially unaffected by capacitive current components provided by transient behavior of the first and second stages.Type: GrantFiled: January 12, 2007Date of Patent: April 21, 2009Assignee: Atmel CorporationInventors: Gabriele Pelli, Lorenzo Bedarida, Massimiliano Frulio, Davide Manfreā²
-
Patent number: 7522002Abstract: A current mirror circuit includes a first current-mirror transistor coupled to a second current-mirror transistor. A load is coupled to the second current-mirror transistor. A first current source is coupled to the first current-mirror transistor to cause a bias current to flow through the first current-mirror transistor and a second current source is coupled to the second current-mirror transistor and in parallel with the load to shunt the bias current away from the load.Type: GrantFiled: January 4, 2007Date of Patent: April 21, 2009Assignee: Atmel CorporationInventors: Gabriele Pelli, Lorenzo Bedarida, Massimiliano Frulio, Andrea Bettini
-
Patent number: 7447071Abstract: A plurality of memory sub-arrays are formed in a p-well region. Each of the memory sub-arrays has at least one first-level column decoder that includes a plurality of low-voltage MOS selector transistors that are also formed within the p-well. A last-level decoder is formed outside of the p-well region and includes high-voltage MOS transistors to provide an output signal to one of an array of sense amplifiers. During a memory erase mode of operation, a high voltage is provided to bias the p-well region and a plurality of high-voltage switches are activated to provide a high voltage to gate terminals of the selector transistor in the first-level column decoders. One or more intermediate-level column decoders are formed as low-voltage selector transistors in the p-well between the first-level column decoder and the last-level column decoder.Type: GrantFiled: November 8, 2006Date of Patent: November 4, 2008Assignee: Atmel CorporationInventors: Massimiliano Frulio, Stefano Surico, Andrea Sacco, Davide Manfre
-
Patent number: 7436232Abstract: A regenerative clock repeater comprises an edge detector and an output driver means to produce the clock signal by recovering its high logical level and low logical level. The output driver means further comprises a pull-up and a pull-down circuitry adapted to receive a pair of control signals. These control signals are generated by the edge detector to sense the rising edge and falling edge of the clock signal. Inside the edge detector, a pair of threshold level detectors detect a high and a low logical level of the clock signal and inputs the results to a combination of logic gates and a latch to keep the locations of the signal markers fixed. These fixed-location of control signals trigger the output driver means to recover the high logical level and the low logical level of said clock signal.Type: GrantFiled: September 17, 2003Date of Patent: October 14, 2008Assignee: Atmel CorporationInventors: Stefano Sivero, Massimiliano Frulio
-
Publication number: 20080246504Abstract: A serial-interface flash memory device includes a data/address I/O pin and a clock input pin. A bidirectional buffer is coupled to the data/address I/O pin. A serial interface logic block including data direction control is coupled to the clock pin, the bidirectional buffer, to internal control logic, and to read-voltage and modify-voltage generators. A first switch is coupled to the read-voltage generator and the clock buffer and a second switch is coupled to the modify-voltage generator and the clock buffer, the first and second switches each having a control input. Memory drivers are coupled to the read-voltage generator and the modify-voltage generator through the first and second switches. First and second registers coupled between the serial interface logic and the first and second switches. A memory array is coupled to the memory drivers and read amplifiers and program buffers are coupled between the serial interface logic and the memory drivers.Type: ApplicationFiled: April 4, 2007Publication date: October 9, 2008Applicant: ATMEL CORPORATIONInventors: Stefano Surico, Marco Passerini, Massimiliano Frulio, Alex Pojer
-
Patent number: 7430150Abstract: A method and system for providing a multi-bank memory is described. The method and system include providing a plurality of banks. Each of the plurality of banks includes at least one array including a plurality of memory cells and analog sensing circuitry. The method and system further include providing common digital sensing circuitry coupled with the plurality of banks.Type: GrantFiled: May 5, 2005Date of Patent: September 30, 2008Assignee: Atmel CorporationInventors: Massimiliano Frulio, Stefano Sivero, Fabio Tassan Caser, Mauro Chinosi
-
Publication number: 20080232169Abstract: A flash memory integrated circuit includes a plurality of flash memory arrays. A global word line driver is associated with each array, each global word line driver coupled to a plurality of select lines. A plurality of sense amplifiers are individually coupled to a plurality of bit lines. A plurality of sub arrays in each array each include a plurality of NAND flash memory cells coupled to local word lines and local bit lines. A local word line driver is associated with each sub-array and coupled to the plurality of select lines and configured to drive ones of the local word lines in its sub array associated with selected ones of the plurality of NAND flash memory cells in its sub-array. A local bit line driver is coupled between selected ones of the local bit lines in each sub array and selected ones of the plurality of bit lines.Type: ApplicationFiled: March 20, 2007Publication date: September 25, 2008Applicant: ATMEL CORPORATIONInventors: Massimiliano Frulio, Lorenzo Bedarida, Simone Bartoli, Fabio Tassan Caser
-
Publication number: 20080170454Abstract: A sense amplifier circuit for reading the state of memory cells. In one aspect of the invention, the sense amplifier circuit includes a first stage receiving a cell current derived from the memory cell and a reference current derived from a reference cell, and a second stage receiving the cell current and the reference current. A comparator, coupled to the first stage and the second stage, provides an output indicative of the state of the memory cell based on a difference of the voltages provided by the first stage and the second stage, where the state indicated by the comparator is substantially unaffected by capacitive current components provided by transient behavior of the first and second stages.Type: ApplicationFiled: January 12, 2007Publication date: July 17, 2008Inventors: Gabriele Pelli, Lorenzo Bedarida, Massimiliano Frulio, Davide Manfre
-
Publication number: 20080164948Abstract: A current mirror circuit includes a first current-mirror transistor coupled to a second current-mirror transistor. A load is coupled to the second current-mirror transistor. A first current source is coupled to the first current-mirror transistor to cause a bias current to flow through the first current-mirror transistor and a second current source is coupled to the second current-mirror transistor and in parallel with the load to shunt the bias current away from the load.Type: ApplicationFiled: January 4, 2007Publication date: July 10, 2008Applicant: Atmel CorporationInventors: Gabriele Pelli, Lorenzo Bedarida, Massimiliano Frulio, Andrea Bettini
-
Publication number: 20080143395Abstract: Apparatus, systems, and methods are disclosed that operate to trigger a reference voltage generator from a supply voltage detector, compare an output voltage level from the reference voltage generator with the a supply voltage, and to generate an enable signal when the supply voltage is greater than the output voltage level. Additional apparatus, systems, and methods are disclosed.Type: ApplicationFiled: December 15, 2006Publication date: June 19, 2008Applicant: ATMEL CORPORATIONInventors: Massimiliano Frulio, Stefano Surico, Andrea Bettini, Monica Marziani
-
Publication number: 20080136500Abstract: A charge pump circuit for generating a plurality of voltages in excess of a supply voltage includes a first group of cascaded charge-pump stages, the input of a first charge pump stage in the first group being driven from the supply voltage. A first output stage has an input driven from the output of a last charge pump stage of the first group and an output coupled to a first voltage node. A second group of cascaded charge-pump stages is provided, the input of the first charge pump stage of the second group being driven from the output of the last charge pump stage of the first group. A second output stage has an input driven from the output of the last charge pump stage in the second group and an output coupled to a second voltage node.Type: ApplicationFiled: December 11, 2006Publication date: June 12, 2008Applicant: Atmel CorporationInventors: Massimiliano Frulio, Stefano Sivero, Marco Passerini, Fabio Tassan Caser
-
Publication number: 20080123415Abstract: A plurality of memory sub-arrays are formed in a p-well region. Each of the memory sub-arrays has at least one first-level column decoder that includes a plurality of low-voltage MOS selector transistors that are also formed within the p-well. A last-level decoder is formed outside of the p-well region and includes high-voltage MOS transistors to provide an output signal to one of an array of sense amplifiers. During a memory erase mode of operation, a high voltage is provided to bias the p-well region and a plurality of high-voltage switches are activated to provide a high voltage to gate terminals of the selector transistor in the first-level column decoders. One or more intermediate-level column decoders are formed as low-voltage selector transistors in the p-well between the first-level column decoder and the last-level column decoder.Type: ApplicationFiled: November 8, 2006Publication date: May 29, 2008Applicant: ATMEL CORPORATIONInventors: Massimiliano Frulio, Stefano Surico, Andrea Sacco, Davide Manfre