Patents by Inventor Massimo V. Fischetti
Massimo V. Fischetti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9741416Abstract: Memory devices based on gate controlled ferromagnetism and spin-polarized current injection are provided. The device structure can include a two dimensional (2D) topological insulator (TI) having an active area body. One or a pair of ferromagnetic storage units are provided on top of the 2D TI with a dielectric and a gate thereon. A first contact can be at one end of the 2D TI and a second contact can be at the other end of the 2D TI, with the one or pair of ferromagnetic storage units on the 2D TI between the two contacts to facilitate 2D TI transport along a one-dimensional edge of the first and/or second lateral side. Application of biases via the gate and the first and second contacts enable read and write operations.Type: GrantFiled: September 12, 2016Date of Patent: August 22, 2017Assignee: Board of Regents, the University of Texas SystemInventors: William G. Vandenberghe, Christopher L. Hinkle, Massimo V. Fischetti
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Patent number: 7968946Abstract: A semiconductor (e.g., complementary metal oxide semiconductor (CMOS)) structure formed on a (110) substrate that has improved performance, in terms of mobility enhancement is provided. In accordance with the present invention, the inventive structure includes at least one of a single tensile stressed liner, a compressively stressed shallow trench isolation (STI) region, or a tensile stressed embedded well, which is used in conjunction with the (110) substrate to improve carrier mobility of both nFETs and pFETs. The present invention also relates to a method of providing such structures.Type: GrantFiled: May 16, 2008Date of Patent: June 28, 2011Assignee: International Business Machines CorporationInventors: Massimo V. Fischetti, Qiqing C. Ouyang
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Patent number: 7943486Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing <110> layer; and creating a biaxial strain in the silicon-containing <110> layer.Type: GrantFiled: May 6, 2008Date of Patent: May 17, 2011Assignee: International Business Machines CorporationInventors: Victor Chan, Massimo V. Fischetti, John M. Hergenrother, Meikei Ieong, Rajesh Rengarajan, Alexander Reznicek, Paul M. Solomon, Chun-yung Sung, Min Yang
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Patent number: 7462525Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing <110> layer; and creating a biaxial strain in the silicon-containing <110> layer.Type: GrantFiled: October 25, 2007Date of Patent: December 9, 2008Assignee: International Business Machines CorporationInventors: Victor Chan, Massimo V. Fischetti, John M. Hergenrother, Meikei Ieong, Rajesh Rengarajan, Alexander Reznicek, Paul M. Solomon, Chun-yung Sung, Min Yang
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Publication number: 20080217691Abstract: A semiconductor (e.g., complementary metal oxide semiconductor (CMOS)) structure formed on a (110) substrate that has improved performance, in terms of mobility enhancement is provided. In accordance with the present invention, the inventive structure includes at least one of a single tensile stressed liner, a compressively stressed shallow trench isolation (STI) region, or a tensile stressed embedded well, which is used in conjunction with the (110) substrate to improve carrier mobility of both nFETs and pFETs. The present invention also relates to a method of providing such structures.Type: ApplicationFiled: May 16, 2008Publication date: September 11, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Massimo V. Fischetti, Qiqing C. Ouyang
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Publication number: 20080206958Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing <110> layer; and creating a biaxial strain in the silicon-containing <110> layer.Type: ApplicationFiled: May 6, 2008Publication date: August 28, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Victor Chan, Massimo V. Fischetti, John M. Hergenrother, Meikei Ieong, Rajesh Rengarajan, Alexander Reznicek, Paul M. Solomon, Chun-yung Sung, Min Yang
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Patent number: 7314790Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing <110> layer; and creating a biaxial strain in the silicon-containing <110> layer.Type: GrantFiled: December 18, 2006Date of Patent: January 1, 2008Assignee: International Business Machines CorporationInventors: Victor Chan, Massimo V. Fischetti, John M. Hergenrother, Meikei Ieong, Rajesh Rengarajan, Alexander Reznicek, Paul M. Solomon, Chun-yung Sung, Min Yang
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Patent number: 7161169Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing <110> layer; and creating a biaxial strain in the silicon-containing <110> layer.Type: GrantFiled: November 3, 2004Date of Patent: January 9, 2007Assignee: International Business Machines CorporationInventors: Victor Chan, Massimo V. Fischetti, John M. Hergenrother, Meikei Leong, Rajesh Rengarajan, Alexander Reznicek, Paul M. Solomon, Chun-yung Sung, Min Yang
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Patent number: 6864520Abstract: A method (and structure) for an electronic chip having at least one layer of material for which a carrier mobility of a first carrier type is higher in a first crystal surface than in a second crystal surface and for which a carrier mobility of a second carrier type is higher in the second crystal surface than the first crystal surface includes a first device having at least one component fabricated on the first crystal surface of the material, wherein an activity of the component of the first device involves primarily the first carrier type, and a second device having at least one component fabricated on the second crystal surface of the material, wherein an activity of the component of the second device involves primarily the second carrier type.Type: GrantFiled: April 4, 2002Date of Patent: March 8, 2005Assignee: International Business Machines CorporationInventors: Massimo V. Fischetti, Steven E. Laux, Paul M. Solomon, Hon-Sum Philip Wong
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Publication number: 20030190791Abstract: A method (and structure) for an electronic chip having at least one layer of material for which a carrier mobility of a first carrier type is higher in a first crystal surface than in a second crystal surface and for which a carrier mobility of a second carrier type is higher in the second crystal surface than the first crystal surface includes a first device having at least one component fabricated on the first crystal surface of the material, wherein an activity of the component of the first device involves primarily the first carrier type, and a second device having at least one component fabricated on the second crystal surface of the material, wherein an activity of the component of the second device involves primarily the second carrier type.Type: ApplicationFiled: April 4, 2002Publication date: October 9, 2003Applicant: International Business Machines CorporationInventors: Massimo V. Fischetti, Steven E. Laux, Paul M. Solomon, Hon-Sum Philip Wong