Abstract: Apparatuses, systems, methods, and computer program products are disclosed for triggering untriggered assertions in design verification. A method includes determining one or more assertions of a plurality of assertions that are not triggered while validating one or more behaviors of an integrated circuit (“IC”) design. A plurality of assertions may be intended to test a validity of one or more behaviors of an IC design. A method includes determining one or more dependencies for one or more untriggered assertions. One or more dependencies for an untriggered assertion may affect how an assertion is triggered. A method includes generating one or more testing scenarios for an IC design, based on one or more dependencies, for triggering one or more untriggered assertions.

Abstract: A synchronous dynamic random access memory controller has a high speed interface and a low speed interface. The high speed interface has a buffer with entries for receiving transactions, and the buffer has a valid bit for each entry. The entries store transactions that are received from a high speed bus. The low speed interface retrieves transactions from the buffer. The high speed interface and low speed interface each have state machines that synchronize the high speed and low speed interfaces using the valid bit for each of the entries.

Abstract: A synchronous dynamic random access memory controller has a high speed interface and a low speed interface. The high speed interface has a buffer with entries for receiving transactions, and the buffer has a valid bit for each entry. The entries store transactions that are received from a high speed bus. The low speed interface retrieves transactions from the buffer. The high speed interface and low speed interface each have state machines that synchronize the high speed and low speed interfaces using the valid bit for each of the entries.

Abstract: A synchronous dynamic random access memory controller has a high speed interface and a low speed interface. The high speed interface has a buffer with entries for receiving transactions, and the buffer has a valid bit for each entry. The entries store transactions that are received from a high speed bus. The low speed interface retrieves transactions from the buffer. The high speed interface and low speed interface each have state machines that synchronize the high speed and low speed interfaces using the valid bit for each of the entries.

Abstract: A computer system includes a bus interface with a plurality of data buffers. Each data buffer is clocked by an individual clock signal. To reduce the power consumption of the bus interface unit, the clock signals of the data buffers that are inactive are disabled during the period of inactivity. The bus interface unit includes a clock control unit that monitors a data bus coupled to the bus interface to determine when a bus cycle begins and the type of bus cycle. The clock control unit additionally monitors memory and CPU buffer signals that indicate which, if any, buffers are being accessed by the memory or CPU. From this information, the clock control unit determines which buffers are active and inactive, and outputs control signals to a clock unit to disable the clock signals associated with inactive buffers.