Abstract: A substantially ohmic substrate contact may be formed in an SOI semiconductor device by using a conductive material, such as aluminum, for the substrate contact that forms an ohmic contact even at low dopant concentrations, usually encountered in SOI substrates. Moreover, a process sequence is disclosed that allows the formation of the ohmic substrate contact at a high degree of compatibility with conventional dual contact approaches.

Abstract: A semiconductor device manufacturing method is provided where a device structure is formed on top of a wafer that comprises a backside semiconductor substrate, a buried insulator layer and a top semiconductor layer. Then, an etch stop layer is formed upon the wafer that carries the device structure, and a window is formed in the etch stop layer. Further, a dielectric layer is formed upon the etch stop layer that has the window. Then, a first contact hole through the dielectric layer and the window down to the backside semiconductor substrate is simultaneously etched with at least one second contact hole through the dielectric layer down to the device structure. The wafer may be a silicon-on-insulator (SOI) wafer, and the etch stop layer and the dielectric layer may be formed by depositing silicon oxynitride and tetraethyl orthosilicate (TEOS), respectively. The device structure may be a CMOS transistor structure.

Abstract: The effect of resist poisoning may be eliminated or at least substantially reduced in the formation of a low-k metallization layer, in that a nitrogen-containing barrier/etch stop layer is provided with a significantly reduced nitrogen concentration at an interface in contact with said low-k dielectric material. Consequently, diffusion of nitrogen and nitrogen compounds in vias formed in said low-k dielectric layer is significantly suppressed, so that in a subsequent photolithographic step, interaction of nitrogen and nitrogen compounds with the photoresist is remarkably reduced.

Abstract: A method is provided, the method including forming a gate dielectric above a substrate layer, and forming a gate conductor above the gate dielectric. The method also includes forming at least one dielectric isolation structure in the substrate adjacent the gate dielectric.

Abstract: A method is presented to increase, by means of dummy via or contact structures, the open areas to 5% or more of the total wafer area in a semiconductor manufacturing process, e.g., contact/via etch processes for interconnect layers. An open area of 5% or more allows robust endpoint detection using optical emission from the plasma, or electrical signals from the RF system. An end-pointed via/contact etch process overcomes the problems encountered due to the effects of aspect-ratio dependent etching, etch rate differences between tools, etch rate fluctuations over time, and deviations of mean incoming film thickness. With end-pointed etching, only the sources of non-uniformity over the wafer have to be considered during etch, which reduces the amount of over-etch built into a conventional via/contact etch process. The dummy structures may be redundant (functional) structures or “true” dummy (non-functional) structures. The dummy structures have the same size as functional structures.

Abstract: Various circuit structures incorporating masks and anti-reflective coatings and methods of fabricating the same are provided. In one aspect, a circuit structure is provided that includes a substrate and a first photosensitive film on the substrate. The first photosensitive film is photosensitive to a first electromagnetic spectrum and anti-reflective of a second electromagnetic spectrum that differs from the first electromagnetic spectrum. A second photosensitive film is on the first photosensitive film. The second photosensitive film is photosensitive to the second electromagnetic spectrum whereby exposure by the second electromagnetic spectrum will activate the second photosensitive film but not the first photosensitive film and exposure by the first electromagnetic spectrum will activate unmasked portions of the first photosensitive film. The first photosensitive film doubles as an anti-reflective coating that may be patterned anisotropically using lithographic techniques.

Abstract: A method for forming an integrated circuit includes etching a first opening to a first depth in a dielectric material over a semiconductor device on a first semiconductor substrate and etching a second opening to a second depth in the dielectric material over the first semiconductor substrate. The first and second openings are differently sized to respectively etch to the first and second depths in about the same time due to etch lag. The first and second openings are filled with conductive material.

Abstract: An SOI substrate includes a diffusion barrier layer, the layer thickness and composition of which is selected so as to substantially prevent copper atoms and ions from diffusing through the diffusion barrier layer. The diffusion barrier layer is located to substantially reduce the deleterious effect of copper that may be introduced into a semiconductor device from the back side of the substrate during various manufacturing stages of the semiconductor device. In one particular example, a silicon wafer with a silicon nitride layer as a diffusion barrier layer and a silicon wafer with an oxide layer is bonded. After separation, an SOI substrate is obtained that has superior characteristics with respect to resistance against copper back side diffusion.

Abstract: The present invention relates to a method of forming contacts of semiconductor devices manufactured on silicon-on-oxide (SOI) wafers. According to the method of the present invention, a heavily doped region is formed in the backside silicon layer during the manufacturing process and a backside contact to the heavily doped region is provided at the end of the manufacturing process. The backside contact exhibits nearly ohmic characteristics avoiding the drawbacks arising from Schottky backside contacts as formed with the usual prior art methods. Moreover, a transistor including a backside contact with an ohmic substrate contact junction is disclosed.

Abstract: The present invention is directed to a method of forming halo implants in a semiconductor device. In one illustrative embodiment, the method comprises forming a gate electrode above a surface of a semiconducting substrate, and forming a hard mask layer above the gate electrode and the substrate. The method further comprises patterning the hard mask layer to define an opening in the hard mask layer, and performing an angled implantation process through the opening in the hard mask to introduce dopant atoms into the substrate under at least a portion of the gate electrode.

Abstract: A method is provided, the method including forming a gate dielectric above a surface of the substrate, forming the conductive gate structure above the gate dielectric, the conductive gate structure having an edge region, and forming a source/drain extension (SDE) adjacent the conductive gate structure. The method also includes forming a dopant-depleted-SDE region in the substrate under the edge region of the conductive gate structure.

Abstract: The present invention is directed to a method of forming halo implants in a semiconductor device. In one illustrative embodiment, the method comprises forming a structure above a semiconducting substrate, forming a layer of photoresist above the structure and the substrate, and positioning the substrate in an exposure tool that has a light source and a focal plane. The method further comprises positioning the surface of the layer of photoresist in an exposure plane that is different from the focal plane of the exposure tool, exposing the photoresist to the light source of the exposure tool while the surface of the photoresist is in the exposure plane, and developing the layer of photoresist to define an opening in the layer of photoresist around the structure on the substrate.

Abstract: With standard DUV lithography technology it is not easy to achieve MOS transistor gates in sub-100 nm range. With the method of trim-etching in HI/O2 plasmas there is an opportunity to use the current lithography tools, to reduce the dimensions of the resist feature, and to achieve sub-100 nm MOS transistor gates for advanced devices. The method of trim-etching in HI/O2 plasmas delivers another factor to control the critical dimension of the MOS devices very accurately. Therefore, this invention helps to significantly reduce the total cost for manufacturing small MOS devices with a critical dimension in the sub-100 nm range.

Abstract: A method is provided, the method including forming a gate dielectric layer above a substrate layer, forming a gate conductor layer above the gate dielectric layer, forming a first hard mask layer above the gate conductor layer, and forming a second hard mask layer above the first hard mask layer. The method also includes forming a trimmed photoresist mask above the second hard mask layer, and forming a patterned hard mask in the second hard mask layer using the trimmed photoresist mask to remove portions of the second hard mask layer, the patterned hard mask having a first dimension. The method further includes forming a selectively etched hard mask in the first hard mask layer by removing portions of the first hard mask layer adjacent the patterned hard mask, the selectively etched hard mask having a second dimension less than the first dimension, and forming a gate structure using the selectively etched hard mask to remove portions of the gate conductor layer above the gate dielectric layer.

Abstract: With standard DUV lithography technology it is not easy to achieve MOS transistor gates in sub−100 nm range. With the method of trim-etching in HI/O2 plasmas there is an opportunity to use the current lithography tools, to reduce the dimensions of the resist feature, and to achieve sub−100 nm MOS transistor gates for advanced devices. The method of trim-etching in HI/O2 plasmas delivers another factor to control the critical dimension of the MOS devices very accurately. Therefore, this invention helps to significantly reduce the total cost for manufacturing small MOS devices with a critical dimension in the sub−100 nm range.