Abstract: An 8-transistor (8T) static random access memory (SRAM) cell is provided. The SRAM cell includes a first inverter and a second inverter that are cross-coupled to define first and second storage nodes. The SRAM cell also includes a first access transistor controlled by a write word line, wherein the first access transistor is configured to couple the first storage node to a write bit line when the write word line is activated. The SRAM cell further includes a second access transistor controlled by a read word line, wherein the second access transistor is configured to couple the second storage node to the read bit line through a third inverter when the read word line is activated. The third inverter is configured to charge the read bit line so that a pre-charging circuit is not required. In the SRAM cell, the reading and writing operations are electrically separated to lower power consumption, improve noise margin, and provide other advantages compared to existing SRAM cell designs.

Abstract: Combining the functionality of sleep transistors with logic devices in power-gating circuits by utilizing fully depleted silicon-on-insulator (FDSOI) transistors. In an embodiment, a back gate of a FDSOI transistor controls the threshold voltage to eliminate the need for standalone sleep transistors.

Abstract: Combining the functionality of sleep transistors with logic devices in power-gating circuits by utilizing fully depleted silicon-on-insulator (FDSOI) transistors. In an embodiment, a back gate of a FDSOI transistor controls the threshold voltage to eliminate the need for standalone sleep transistors.