Patents by Inventor Masumi Yoshida

Masumi Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8829521
    Abstract: Provided is a TFT board for a liquid crystal display device including: a circuit layer formed on a substrate, the circuit layer including a thin film transistor including a semiconductor layer, a gate electrode, a drain electrode, and a source electrode; and a color filter layer formed on the circuit layer. The color filter layer has a through hole formed therein above the semiconductor layer in a region between the source electrode and the drain electrode.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: September 9, 2014
    Assignee: Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Tetsuya Kawamura, Masumi Yoshida
  • Publication number: 20110233552
    Abstract: Provided is a TFT board for a liquid crystal display device including: a circuit layer formed on a substrate, the circuit layer including a thin film transistor including a semiconductor layer, a gate electrode, a drain electrode, and a source electrode; and a color filter layer formed on the circuit layer. The color filter layer has a through hole formed therein above the semiconductor layer in a region between the source electrode and the drain electrode.
    Type: Application
    Filed: December 15, 2010
    Publication date: September 29, 2011
    Applicant: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
    Inventors: Tetsuya KAWAMURA, Masumi YOSHIDA
  • Patent number: 7775402
    Abstract: A dispensing container with a pump includes a neck, a manual pump of a push-down type disposed in the neck, a push-down head fitted to the top of the pump, and a cap having an attaching cylinder fitted around the neck. A rotary cylinder is disposed on the outside of the attaching cylinder coaxially on central axis. A cover cylinder having a cover wall is disposed coaxially between the attaching cylinder and the rotary cylinder in a manner capable of going up and down under the condition that an elevating system has been established with the attaching cylinder and the rotary cylinder by the rotary movement of the rotary attachment. The cover cylinder is disposed so the push-down head is exposed out of the cover cylinder at its lower-limit position and cannot be pushed down at the upper-limit position of the cover cylinder to prevent contents from being erroneously discharged.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: August 17, 2010
    Assignees: The Procter and Gamble Company, Yoshino Kogyosho Co, Ltd.
    Inventors: Masumi Yoshida, Chiaki Kamimura, Tsutomu Kobayashi
  • Publication number: 20090011568
    Abstract: An FTI structure is employed in an isolation region making contact in a Y direction with a P-type impurity region serving as a drain region of a PMOS transistor. First, second and third N-type impurity layers serving as body regions are connected to a high potential line via fourth, fifth and sixth N-type impurity layers, respectively, and further via a seventh N-type impurity layer. The fourth to sixth N-type impurity layers are provided between an insulating layer of an SOI substrate and an element isolation insulating film in a PTI region.
    Type: Application
    Filed: September 9, 2008
    Publication date: January 8, 2009
    Applicant: Renesas Technology Corp.
    Inventors: Toshiki KANAMOTO, Masumi Yoshida, Tetsuya Watanabe, Takashi Ippoushi
  • Patent number: 7432581
    Abstract: An FTI structure is employed in an isolation region making contact in a Y direction with a P-type impurity region serving as a drain region of a PMOS transistor. First, second and third N-type impurity layers serving as body regions are connected to a high potential line via fourth, fifth and sixth N-type impurity layers, respectively, and further via a seventh N-type impurity layer. The fourth to sixth N-type impurity layers are provided between an insulating layer of an SOI substrate and an element isolation insulating film in a PTI region.
    Type: Grant
    Filed: January 23, 2006
    Date of Patent: October 7, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Toshiki Kanamoto, Masumi Yoshida, Tetsuya Watanabe, Takashi Ippoushi
  • Publication number: 20070246484
    Abstract: A dispensing container with a pump is provided, which comprises a neck standing in the upper portion of container and having a manual pump of a push-down type disposed upright in the neck; a push-down head fitted to the top of the pump; a cap having an attaching cylinder fitted around said neck and having said pump fitted and secured to the neck in a sealed state; a rotary attachment having its lower portion fitted around the lower portion of the cap in a rotatable manner and having a rotary cylinder disposed on the outside of the attaching cylinder coaxially on central axis; and a cover cylinder having a cover wall disposed coaxially between the attaching cylinder and the rotary cylinder in a manner capable of going up and down under the condition that an elevating system has been established with the attaching cylinder and the rotary cylinder by the rotary movement of the rotary attachment, wherein said cover cylinder is set up in such a way that the push-down head is exposed out of the cover cylinder at it
    Type: Application
    Filed: December 20, 2005
    Publication date: October 25, 2007
    Applicants: The Procter and Gamble Company, Yoshino Kogyosho Co., Ltd.
    Inventors: Masumi Yoshida, Chiaki Kamimura, Tsutomu Kobayashi
  • Publication number: 20060170052
    Abstract: An FTI structure is employed in an isolation region making contact in a Y direction with a P-type impurity region serving as a drain region of a PMOS transistor. First, second and third N-type impurity layers serving as body regions are connected to a high potential line via fourth, fifth and sixth N-type impurity layers, respectively, and further via a seventh N-type impurity layer. The fourth to sixth N-type impurity layers are provided between an insulating layer of an SOI substrate and an element isolation insulating film in a PTI region.
    Type: Application
    Filed: January 23, 2006
    Publication date: August 3, 2006
    Applicant: Renesas Technology Corp.
    Inventors: Toshiki Kanamoto, Masumi Yoshida, Tetsuya Watanabe, Takashi Ippoushi
  • Patent number: 6113475
    Abstract: A method of cleaning a container and an apparatus therefor for cleaning a surface layer of the container by blasting fine particles of sodium bicarbonate with pressurized air into the container. The apparatus provdes a ball joint construction and a nozzle angle control mechanism for swing a nozzle body at an angle within a range of 50 degrees.
    Type: Grant
    Filed: September 30, 1999
    Date of Patent: September 5, 2000
    Assignee: Daiko Electric Co., Ltd.
    Inventors: Takayuki Masuda, Kiyoyuki Okamoto, Masumi Yoshida
  • Patent number: 4561106
    Abstract: Disclosed herein is a character recognition process which extracts white regions surrounded by strokes of character pattern information and recognizes characters by determining the directions in which said white regions are opened. The process is provided by processing apparatus, for conversion of mesh information, disposed so as to convert a white mesh point present between two black mesh points to a black mesh point during one scanning period for scanning said character pattern information in one direction. The directions of openings of the white regions are determined based on the converted character pattern information obtained by the processing apparatus.
    Type: Grant
    Filed: May 7, 1985
    Date of Patent: December 24, 1985
    Assignee: Fujitsu Limited
    Inventors: Masumi Yoshida, Takeshi Masui
  • Patent number: 4105998
    Abstract: A pattern recognition processing system in which variations in a character, pattern or the like, especially in a handwritten one, are suppressed to extract its invariable characteristics, ensuring accurate recognition of the character, pattern or the like. The pattern to be recognized is divided into circumscribed quadrangular areas and scanned in horizontal and vertical directions to extract reflection segments between the vertical frames of the circumscribed quadrangular areas and particular segments between adjacent ones of pattern strokes. Further, endpoints of these reflection and particular segments are checked in directions across the scanning directions to extract those endpoints which are not blocked by the pattern strokes, and the corresponding positions of the co-ordinates of these endpoints on a figure frame in the directions across the scanning directions are encoded to extract characteristics of contours of the pattern to be recognized.
    Type: Grant
    Filed: March 22, 1977
    Date of Patent: August 8, 1978
    Assignee: Fujitsu Limited
    Inventors: Masumi Yoshida, Kiyoshi Iwata, Eiichiro Yamamoto, Takeshi Masui, Yukikazu Kabuyama
  • Patent number: D446012
    Type: Grant
    Filed: June 6, 2000
    Date of Patent: August 7, 2001
    Assignee: The Procter & Gamble Company
    Inventors: Akiko Ashiwa, Masumi Yoshida
  • Patent number: D523350
    Type: Grant
    Filed: June 21, 2005
    Date of Patent: June 20, 2006
    Assignee: The Procter & Gamble Company
    Inventors: Miwa Ohmoto, Masumi Yoshida
  • Patent number: D483527
    Type: Grant
    Filed: December 11, 2002
    Date of Patent: December 9, 2003
    Assignee: The Procter & Gamble Company
    Inventors: Akiko Ashiwa, Masumi Yoshida, Kenji Tanihata, Masataka Sugita, Teruhisa Hirano, Satoshi Yamane