Patents by Inventor Masuzumi Shiochi

Masuzumi Shiochi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Interface circuit and interface circuit delay time controlling method
    Patent number: 6294944
    Abstract: An interface cell transmits a signal with a delay time corresponding to a delay time control signal. A delay time control circuit consists of a delay chain and a PLL circuit. The delay chain consists of a plurality of series-connected interface cells to a head cell of which a clock signal is supplied, and a delay signal of a clock signal is then fetched from the interface cell at an arbitrary stage. The PLL circuit generates a delay time control signal so as to make phase difference between the clock signal and the delay signal equal. This is true of a delay cell. A phase difference compensation circuit is provided on an output end of a clock line of the integrated circuit to delay an input clock signal based on an input control signal.
    Type: Grant
    Filed: January 31, 2000
    Date of Patent: September 25, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masuzumi Shiochi, Kanji Egawa
  • Interface circuit and interface circuit delay time controlling method
    Patent number: 6081146
    Abstract: An interface cell transmits a signal with a delay time corresponding to a delay time control signal. A delay time control circuit consists of a delay chain and a PLL circuit. The delay chain consists of a plurality of series-connected interface cells to a head cell of which a clock signal is supplied, and a delay signal of a clock signal is then fetched from the interface cell at an arbitrary stage. The PLL circuit generates a delay time control signal so as to make phase difference between the clock signal and the delay signal equal. This is true of a delay cell. A phase difference compensation circuit is provided on an output end of a clock line of the integrated circuit to delay an input clock signal based on an input control signal.
    Type: Grant
    Filed: September 24, 1997
    Date of Patent: June 27, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masuzumi Shiochi, Kanji Egawa