Patents by Inventor Mathew Arcoleo

Mathew Arcoleo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • READ CACHE MEMORY
    Publication number: 20200363962
    Abstract: The present disclosure includes methods and apparatuses for read cache memory. One apparatus includes a read cache memory apparatus comprising a first DRAM array, a first and a second NAND array, and a controller configured to manage movement of data between the DRAM array and the first NAND array, and between the first NAND array and the second NAND array.
    Type: Application
    Filed: August 6, 2020
    Publication date: November 19, 2020
    Inventors: Eugene Feng, Mathew Arcoleo
  • Data movement between volatile and non-volatile memory in a read cache memory
    Patent number: 10768828
    Abstract: The present disclosure includes methods and apparatuses for read cache memory. One apparatus includes a read cache memory apparatus comprising a first DRAM array, a first and a second NAND array, and a controller configured to manage movement of data between the DRAM array and the first NAND array, and between the first NAND array and the second NAND array.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: September 8, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Eugene Feng, Mathew Arcoleo
  • READ CACHE MEMORY
    Publication number: 20170277449
    Abstract: The present disclosure includes methods and apparatuses for read cache memory. One apparatus includes a read cache memory apparatus comprising a first DRAM array, a first and a second NAND array, and a controller configured to manage movement of data between the DRAM array and the first NAND array, and between the first NAND array and the second NAND array.
    Type: Application
    Filed: June 12, 2017
    Publication date: September 28, 2017
    Inventors: Eugene Feng, Mathew Arcoleo
  • Read cache memory with DRAM class promotion
    Patent number: 9710173
    Abstract: The present disclosure includes methods and apparatuses for read cache memory. One apparatus includes a read cache memory apparatus comprising a first DRAM array, a first and a second NAND array, and a controller configured to manage movement of data between the DRAM array and the first NAND array, and between the first NAND array and the second NAND array.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: July 18, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Eugene Feng, Mathew Arcoleo
  • READ CACHE MEMORY
    Publication number: 20150339064
    Abstract: The present disclosure includes methods and apparatuses for read cache memory. One apparatus includes a read cache memory apparatus comprising a first DRAM array, a first and a second NAND array, and a controller configured to manage movement of data between the DRAM array and the first NAND array, and between the first NAND array and the second NAND array.
    Type: Application
    Filed: May 20, 2014
    Publication date: November 26, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Eugene Feng, Mathew Arcoleo
  • Programmably timed storage element for integrated circuit input/output
    Patent number: 6167528
    Abstract: A programmable skew buffer for optimizing the timing at the input or output pins of a memory device. The timing at each input and output pin of the memory device can be adjusted on an independent basis by coupling each input or output pin to a separate programmable skew buffer. The programmable skew buffer includes a clocked storage element that receives data from an input pin and outputs data to the memory array in the memory device when optimizing the input timing of the memory device, or receives data from the memory array in the memory device and outputs data to an output pin when optimizing the output timing of the memory device. The programmable skew buffer also includes a programmable delay circuit which generates one of a plurality of clock signals wherein each signal represents a delayed version of the system clock.
    Type: Grant
    Filed: December 21, 1995
    Date of Patent: December 26, 2000
    Assignee: Cypress Semiconductor
    Inventor: Mathew Arcoleo