Patents by Inventor Matt Allison
Matt Allison has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240063785Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.Type: ApplicationFiled: September 13, 2023Publication date: February 22, 2024Inventors: Simon Edward Willard, Tero Tapio Ranta, Matt Allison, Shashi Ketan Samal
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Publication number: 20240063789Abstract: A FET switch stack and a method to operate a FET switch stack. The FET switch stack includes a stacked arrangement of body bypass FET switches connected across respective common body resistors. The body bypass FET switches bypass the respective common body resistors during the OFF steady state of the FET switch stack and do not bypass the respective common body resistors during the ON steady state.Type: ApplicationFiled: September 25, 2023Publication date: February 22, 2024Inventors: Eric S. SHAPIRO, Ravindranath D. SHRIVASTAVA, Fleming LAM, Matt ALLISON
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Patent number: 11870431Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.Type: GrantFiled: August 9, 2022Date of Patent: January 9, 2024Assignee: pSemi CorporationInventors: Simon Edward Willard, Tero Tapio Ranta, Matt Allison, Shashi Ketan Samal
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Patent number: 11670555Abstract: Method and devices to reduce integrated circuit fabrication process yield loss due to undesired interactions between PCMs and the wafer test probes during wafer sorting tests are disclosed. The described methods entail the use of a properly patterned metal layer on the PCM dies adjacent to the product dies under test. Such patterned metal layers shield traces of the wafer probes from the circuits of the PCM dies. Various exemplary metal layer patterns are also presented.Type: GrantFiled: December 18, 2020Date of Patent: June 6, 2023Assignee: PSEMI CORPORATIONInventors: Jacob Hamilton, Tran Kononova, Jay Kothari, Matt Allison, Kim T. Nguyen, Eric S. Shapiro
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Publication number: 20230142322Abstract: Devices and methods to manufacture a stack of FET switches in presence of a neighboring stack of FET switches are described. The stack of FET switches is designed or manufactured so that at least its top FET has a width that is smaller than the width of its bottom FET. Other voltage handling configurations and distributions of widths are described.Type: ApplicationFiled: November 10, 2021Publication date: May 11, 2023Inventors: Shashi SAMAL, Matt ALLISON
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Publication number: 20230032891Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.Type: ApplicationFiled: August 9, 2022Publication date: February 2, 2023Inventors: Simon Edward Willard, Tero Tapio Ranta, Matt Allison, Shashi Ketan Samal
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Publication number: 20220257298Abstract: Devices and methods for treating conditions such as rhinitis are disclosed herein where a distal end of a probe shaft is introduced through the nasal cavity where the distal end has an end effector with a first configuration having a low-profile which is shaped to manipulate tissue within the nasal cavity. The distal end may be positioned into proximity of a nasal tissue region having at least one nasal nerve. Once suitably positioned, the distal end may be reconfigured from the first configuration to a second configuration which is shaped to contact and follow the nasal tissue region and the at least one nasal nerve may then be ablated via the distal end. Ablation may be performed using various mechanisms, such as cryotherapy, and optionally under direct visualization.Type: ApplicationFiled: July 8, 2020Publication date: August 18, 2022Inventors: William Jason Fox, Vahid Saadat, David Moosavi, Sherwin Llamido, Roman Turovskiy, William Gould, Matt Allison Herron
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Patent number: 11418183Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.Type: GrantFiled: May 20, 2021Date of Patent: August 16, 2022Assignee: pSemi CorporationInventors: Simon Edward Willard, Tero Tapio Ranta, Matt Allison, Shashi Ketan Samal
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Patent number: 11405034Abstract: A FET switch stack and a method to operate a FET switch stack. The FET switch stack includes a stacked arrangement of body bypass FET switches connected across respective common body resistors. The body bypass FET switches bypass the respective common body resistors during the OFF steady state of the FET switch stack and do not bypass the respective common body resistors during the ON steady state.Type: GrantFiled: May 14, 2021Date of Patent: August 2, 2022Assignee: PSEMI CORPORATIONInventors: Eric S. Shapiro, Ravindranath D. Shrivastava, Fleming Lam, Matt Allison
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Publication number: 20220199475Abstract: Method and devices to reduce integrated circuit fabrication process yield loss due to undesired interactions between PCMs and the wafer test probes during wafer sorting tests are disclosed. The described methods entail the use of a properly patterned metal layer on the PCM dies adjacent to the product dies under test. Such patterned metal layers shield traces of the wafer probes from the circuits of the PCM dies. Various exemplary metal layer patterns are also presented.Type: ApplicationFiled: December 18, 2020Publication date: June 23, 2022Inventors: Jacob HAMILTON, Tran KONONOVA, Jay KOTHARI, Matt ALLISON, Kim T. NGUYEN, Eric S. SHAPIRO
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Publication number: 20210344338Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.Type: ApplicationFiled: May 20, 2021Publication date: November 4, 2021Inventors: Simon Edward Willard, Tero Tapio Ranta, Matt Allison, Shashi Ketan Samal
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Patent number: 10886911Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.Type: GrantFiled: March 28, 2018Date of Patent: January 5, 2021Assignee: pSemi CorporationInventors: Simon Edward Willard, Tero Tapio Ranta, Matt Allison, Shashi Ketan Samal
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Patent number: 10523195Abstract: Embodiments include a switch stack comprising ACS FETs and mixed-style gate resistor bias networks that mitigate the effects of high leakage current. By carefully selecting the number of ACS FETs in a sub-stack that uses a rung gate resistor bias network versus a sub-stack that uses a rail gate resistor bias network, as well as by selecting particularly useful values for the gate resistors in each bias network, a tradeoff can be achieved between adverse Vg offset and Q factor. The switch stack may be configured with rung-rail gate resistor bias networks, or with rung-rail-rung gate resistor bias networks. Other embodiments include mixed-style body resistor bias networks in switch stacks comprising non-ACS FETs. Some embodiments include one or more positive-logic FETs M1-Mn, series-coupled on at least one end to an “end-cap” FET M0 of a type that turns OFF when the applied VGS is essentially zero volts.Type: GrantFiled: August 2, 2018Date of Patent: December 31, 2019Assignee: pSemi CorporationInventors: Yuan Luo, Matt Allison, Eric S. Shapiro
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Publication number: 20190305768Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.Type: ApplicationFiled: March 28, 2018Publication date: October 3, 2019Inventors: Simon Edward Willard, Tero Tapio Ranta, Matt Allison, Shashi Ketan Samal
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Patent number: 10256287Abstract: Embodiments of systems, methods, and apparatus for improving ESD performance and switching time for semiconductor devices including metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on Semiconductor-On-Insulator (“SOI”) and Silicon-On-Sapphire (“SOS”) substrates.Type: GrantFiled: March 2, 2018Date of Patent: April 9, 2019Assignee: pSemi CorporationInventors: Eric S. Shapiro, Matt Allison
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Publication number: 20180308922Abstract: Embodiments of systems, methods, and apparatus for improving ESD performance and switching time for semiconductor devices including metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on Semiconductor-On-Insulator (“SOI”) and Silicon-On-Sapphire (“SOS”) substrates.Type: ApplicationFiled: March 2, 2018Publication date: October 25, 2018Inventors: Eric S. Shapiro, Matt Allison
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Patent number: D933816Type: GrantFiled: July 9, 2019Date of Patent: October 19, 2021Assignee: Arrinex, Inc.Inventors: William Jason Fox, Vahid Saadat, David Moosavi, Sherwin Llamido, Roman Turovskiy, William Gould, Matt Allison Herron
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Patent number: D940856Type: GrantFiled: September 15, 2021Date of Patent: January 11, 2022Assignee: Arrinex, Inc.Inventors: William Jason Fox, Vahid Saadat, David Moosavi, Sherwin Llamido, Roman Turovskiy, William Gould, Matt Allison Herron
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Patent number: D969318Type: GrantFiled: July 9, 2019Date of Patent: November 8, 2022Assignee: Arrinex, Inc.Inventors: William Jason Fox, Vahid Saadat, David Moosavi, Sherwin Llamido, Roman Turovskiy, William Gould, Matt Allison Herron
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Patent number: D990678Type: GrantFiled: October 4, 2022Date of Patent: June 27, 2023Assignee: Arrinex, Inc.Inventors: William Jason Fox, Vahid Saadat, David Moosavi, Sherwin Llamido, Roman Turovskiy, William Gould, Matt Allison Herron