Patents by Inventor Matthew A. Laurent

Matthew A. Laurent has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11961837
    Abstract: In certain examples, methods and semiconductor structures are directed to an integrated circuit (IC) having a diamond layer section and a GaN-based substrate being monolithically integrated or bonded as part of the same IC. In a specific example, the GaN-based substrate includes GaN, AlxGayN (0<x<1; x+y=1) and a dielectric layer, and a diamond layer section which may include polycrystalline diamond. The IC includes: a GaN-based field effect transistor (FET) integrated with a portion of the GaN-based substrate, and a diamond-based FET integrated with a portion of the diamond layer section, the diamond FET being electrically coupled to the GaN-based FET and situated over or against a surface region of the GaN-based substrate.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: April 16, 2024
    Assignees: The Board of Trustees of the Leland Stanford Junior University, The Regents of the University of California
    Inventors: Srabanti Chowdhury, Mohamadali Malakoutian, Matthew A. Laurent, Chenhao Ren, Siwei Li
  • Publication number: 20230031266
    Abstract: In certain examples, methods and semiconductor structures are directed to a method comprising steps of forming by monolithically integrating or seeding via polycrystalline diamond (PCD) particles on a GaN-based layer characterized as including GaN in at least a surface region of the GaN-based layer. After the step of seeding, the PCD particles are grown under a selected pressure to form a diamond layer section and to provide a semi-conductive structure that includes the diamond layer section integrated on or against the surface region of the GaN-based layer.
    Type: Application
    Filed: January 8, 2021
    Publication date: February 2, 2023
    Inventors: Srabanti Chowdhury, Mohamadali Malakoutian, Matthew A. Laurent, Chenhao Ren, Siwei Li
  • Publication number: 20220223586
    Abstract: In certain examples, methods and semiconductor structures are directed to an integrated circuit (IC) having a diamond layer section and a GaN-based substrate being monolithically integrated or bonded as part of the same IC. In a specific example, the GaN-based substrate includes GaN, AlxGayN (0<x<1; x+y=1) and a dielectric layer, and a diamond layer section which may include polycrystalline diamond. The IC includes: a GaN-based field effect transistor (FET) integrated with a portion of the GaN-based substrate, and a diamond-based FET integrated with a portion of the diamond layer section, the diamond FET being electrically coupled to the GaN-based FET and situated over or against a surface region of the GaN-based substrate.
    Type: Application
    Filed: January 7, 2022
    Publication date: July 14, 2022
    Inventors: Srabanti Chowdhury, Mohamadali Malakoutian, Matthew A. Laurent, Chenhao Ren, Siwei Li
  • Publication number: 20210391633
    Abstract: One example includes an integrated circulator system comprising a junction. The junction includes a first port, a second port, and a third port. The junction also includes a substrate material layer on which the first, second, and third ports are provided. The junction also includes a magnetic material layer coupled to the substrate layer. The junction further includes a resonator coupled to the first, second, and third ports to provide signal transmission from the first port to the second port and from the second port to the third port based on a magnetic field provided by the magnetic material layer.
    Type: Application
    Filed: May 14, 2021
    Publication date: December 16, 2021
    Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Matthew A. Laurent, Dino Ferizovic, Benjamin Poust, Kevin A. Matsui
  • Publication number: 20160163846
    Abstract: A method of fabricating a III-nitride semiconductor device, including growing an III-nitride semiconductor and an oxide sequentially to form an oxide/III-nitride interface, without exposure to air in between growth of the oxide and growth of the III-nitride semiconductor.
    Type: Application
    Filed: January 28, 2016
    Publication date: June 9, 2016
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Xiang Liu, Umesh K. Mishra, Stacia Keller, Jeonghee Kim, Matthew Laurent, Jing Lu, Ramya Yeluri, Silvia H. Chan
  • Patent number: 9281183
    Abstract: A method of fabricating a III-nitride semiconductor device, including growing an III-nitride semiconductor and an oxide sequentially to form an oxide/III-nitride interface, without exposure to air in between growth of the oxide and growth of the III-nitride semiconductor.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: March 8, 2016
    Assignee: The Regents of the University of California
    Inventors: Xiang Liu, Umesh K. Mishra, Stacia Keller, Jeonghee Kim, Matthew Laurent, Jing Lu, Ramya Yeluri, Silvia H. Chan
  • Publication number: 20150200286
    Abstract: A method of fabricating a III-nitride semiconductor device, including growing an III-nitride semiconductor and an oxide sequentially to form an oxide/III-nitride interface, without exposure to air in between growth of the oxide and growth of the III-nitride semiconductor.
    Type: Application
    Filed: January 15, 2015
    Publication date: July 16, 2015
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Xiang Liu, Umesh K. Mishra, Stacia Keller, Jeonghee Kim, Matthew Laurent, Jing Lu, Ramya Yeluri, Silvia H. Chan