Abstract: Methods and systems for equalization of a first receiver. A method may include receiving an input signal at the first receiver. The method may also include receiving the input signal at a second receiver. The method may further include determining, from an output response of the second receiver, an estimate of an out-of-channel interferer present in the input signal. The method may also include determining an estimate, of an undesired in-channel response of the first receiver to the out-of-channel interferer present in the input signal. The method may include applying the estimate, of the undesired in-channel response of the first receiver to the out-of-channel interferer present in the input signal, to an output signal of the first receiver to substantially cancel an instance of an undesired in-channel response of the first receiver to the out-of-channel interferer.

Abstract: Methods and systems for equalization of a first receiver. A method may include receiving an input signal at the first receiver. The method may also include receiving the input signal at a second receiver. The method may further include determining, from an output response of the second receiver, an estimate of an out-of-channel interferer present in the input signal. The method may also include determining an estimate, of an undesired in-channel response of the first receiver to the out-of-channel interferer present in the input signal. The method may include applying the estimate, of the undesired in-channel response of the first receiver to the out-of-channel interferer present in the input signal, to an output signal of the first receiver to substantially cancel an instance of an undesired in-channel response of the first receiver to the out-of-channel interferer.

Abstract: Described are a multi-modulus frequency divider and event counter that are based on time-interleaved signals generated from a received signal. For the frequency divider, each time-interleaved clock signal generated from a received clock signal is provided to a bit counter and the output signal from each bit counter is provided to a multiplexer. A multiplexer selection module controls over time which one of the output signals from the bit counters is presented at the output of the multiplexer. The transition frequency of the bits in the time-interleaved clock signals allows various circuit components such as the bit counters to be implemented as CMOS components. Thus the frequency divider is more power-efficient than conventional frequency divider circuits operating at high clock frequencies.

Abstract: Described are a multi-modulus frequency divider and event counter that are based on time-interleaved signals generated from a received signal. For the frequency divider, each time-interleaved clock signal generated from a received clock signal is provided to a bit counter and the output signal from each bit counter is provided to a multiplexer. A multiplexer selection module controls over time which one of the output signals from the bit counters is presented at the output of the multiplexer. The transition frequency of the bits in the time-interleaved clock signals allows various circuit components such as the bit counters to be implemented as CMOS components. Thus the frequency divider is more power-efficient than conventional frequency divider circuits operating at high clock frequencies.

Abstract: Described is a switched-capacitor network and method for performing an analog circuit function. The circuit includes a switched-capacitor network, a comparator, and a voltage-offset network. The switched-capacitor network includes multiple switches, each having a respective threshold voltage and connected to one of a high-limit voltage, a low-limit voltage, and electrical ground. A first comparator input terminal in communication with the switched-capacitor network is configured to receive a node voltage therefrom during a first phase. The second input terminal is configured to receive one of the high-limit voltage and the low-limit voltage. The voltage-offset network provides a voltage shift at the first input terminal setting an input reference level at a mid-level voltage with respect to the high-limit voltage and the low-limit voltage.

Abstract: Described is a switched-capacitor network and method for performing an analog circuit function. The circuit includes a switched-capacitor network, a comparator, and a voltage-offset network. The switched-capacitor network includes multiple switches, each having a respective threshold voltage and connected to one of a high-limit voltage, a low-limit voltage, and electrical ground. A first comparator input terminal in communication with the switched-capacitor network is configured to receive a node voltage therefrom during a first phase. The second input terminal is configured to receive one of the high-limit voltage and the low-limit voltage. The voltage-offset network provides a voltage shift at the first input terminal setting an input reference level at a mid-level voltage with respect to the high-limit voltage and the low-limit voltage.