Patents by Inventor Matthew D. Hendel
Matthew D. Hendel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9772860Abstract: Efficient power management of a system with virtual machines is disclosed. In particular, such efficient power management may enable coordination of system-wide power changes with virtual machines. Additionally, such efficient power management may enable coherent power changes in a system with a virtual machine monitor. Furthermore, such efficient power management may enable dynamic control and communication of power state changes.Type: GrantFiled: September 7, 2016Date of Patent: September 26, 2017Assignee: Microsoft Technology Licensing, LLCInventors: Adrian J. Oney, Bryan Mark Willman, Eric P. Traut, Forrest Curtis Foltz, Matthew D. Hendel, Rene Antonio Vega
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Publication number: 20160378506Abstract: Efficient power management of a system with virtual machines is disclosed. In particular, such efficient power management may enable coordination of system-wide power changes with virtual machines. Additionally, such efficient power management may enable coherent power changes in a system with a virtual machine monitor. Furthermore, such efficient power management may enable dynamic control and communication of power state changes.Type: ApplicationFiled: September 7, 2016Publication date: December 29, 2016Inventors: Adrian J. Oney, Bryan Mark Willman, Eric P. Traut, Forrest Curtis Foltz, Matthew D. Hendel, Rene Antonio Vega
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Patent number: 9489035Abstract: Efficient power management of a system with virtual machines is disclosed. In particular, such efficient power management may enable coordination of system-wide power changes with virtual machines. Additionally, such efficient power management may enable coherent power changes in a system with a virtual machine monitor. Furthermore, such efficient power management may enable dynamic control and communication of power state changes.Type: GrantFiled: December 15, 2015Date of Patent: November 8, 2016Assignee: Microsoft Technology Licensing, LLCInventors: Adrian J. Oney, Bryan Mark Willman, Eric P. Traut, Forrest Curtis Foltz, Matthew D. Hendel, Rene Antonio Vega
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Publication number: 20160109929Abstract: Efficient power management of a system with virtual machines is disclosed. In particular, such efficient power management may enable coordination of system-wide power changes with virtual machines. Additionally, such efficient power management may enable coherent power changes in a system with a virtual machine monitor. Furthermore, such efficient power management may enable dynamic control and communication of power state changes.Type: ApplicationFiled: December 15, 2015Publication date: April 21, 2016Inventors: Adrian J. Oney, Bryan Mark Willman, Eric P. Traut, Forrest Curtis Foltz, Matthew D. Hendel, Rene Antonio Vega
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Patent number: 9218047Abstract: Efficient power management of a system with virtual machines is disclosed. In particular, such efficient power management may enable coordination of system-wide power changes with virtual machines. Additionally, such efficient power management may enable coherent power changes in a system with a virtual machine monitor. Furthermore, such efficient power management may enable dynamic control and communication of power state changes.Type: GrantFiled: December 8, 2014Date of Patent: December 22, 2015Assignee: Microsoft Technology Licensing, LLCInventors: Adrian J. Oney, Bryan Mark Willman, Eric P. Traut, Forrest Curtis Foltz, Matthew D. Hendel, Rene Antonio Vega
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Patent number: 9104594Abstract: Various mechanisms are disclosed for improving the operational efficiency of a virtual translation look-aside buffer (TLB) in a virtual machine environment. For example, one mechanism fills in entries in a shadow page table (SPT) and additionally, speculatively fills in other entries in the SPT based on various heuristics. Another mechanism allows virtual TLBs (translation look-aside buffers) to cache partial walks in a guest page table tree. Still another mechanism allows for dynamic resizing of the virtual TLB to optimize for run-time characteristics of active workloads. Still another mechanism allows virtual machine monitors (VMMs) to support legacy and enlightened modes of virtual TLB operation. Finally, another mechanism allows the VMM to remove only the stale entries in SPTs when linking or switching address spaces. All these mechanisms, together or in part, increase the operational efficiency of the virtual TLB.Type: GrantFiled: December 23, 2013Date of Patent: August 11, 2015Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Ernest S. Cohen, John Te-Jui Sheu, Landy Wang, Matthew D. Hendel, Rene Antonio Vega, Sharvil A. Nanavati
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Publication number: 20150143149Abstract: Efficient power management of a system with virtual machines is disclosed. In particular, such efficient power management may enable coordination of system-wide power changes with virtual machines. Additionally, such efficient power management may enable coherent power changes in a system with a virtual machine monitor. Furthermore, such efficient power management may enable dynamic control and communication of power state changes.Type: ApplicationFiled: December 8, 2014Publication date: May 21, 2015Inventors: Adrian J. Oney, Bryan Mark Willman, Eric P. Traut, Forrest Curtis Foltz, Matthew D. Hendel, Rene Antonio Vega
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Patent number: 8909946Abstract: Efficient power management of a system with virtual machines is disclosed. In particular, such efficient power management may enable coordination of system-wide power changes with virtual machines. Additionally, such efficient power management may enable coherent power changes in a system with a virtual machine monitor. Furthermore, such efficient power management may enable dynamic control and communication of power state changes.Type: GrantFiled: May 18, 2006Date of Patent: December 9, 2014Assignee: Microsoft CorporationInventors: Adrian J. Oney, Bryan Mark Willman, Eric P. Traut, Forrest Curtis Foltz, Matthew D. Hendel, Rene Antonio Vega
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Publication number: 20140122830Abstract: Various mechanisms are disclosed for improving the operational efficiency of a virtual translation look-aside buffer (TLB) in a virtual machine environment. For example, one mechanism fills in entries in a shadow page table (SPT) and additionally, speculatively fills in other entries in the SPT based on various heuristics. Another mechanism allows virtual TLBs (translation look-aside buffers) to cache partial walks in a guest page table tree. Still another mechanism allows for dynamic resizing of the virtual TLB to optimize for run-time characteristics of active workloads. Still another mechanism allows virtual machine monitors (VMMs) to support legacy and enlightened modes of virtual TLB operation. Finally, another mechanism allows the VMM to remove only the stale entries in SPTs when linking or switching address spaces. All these mechanisms, together or in part, increase the operational efficiency of the virtual TLB.Type: ApplicationFiled: December 23, 2013Publication date: May 1, 2014Applicant: Microsoft CorporationInventors: Ernest S. Cohen, John Te-Jui Sheu, Landy Wang, Matthew D. Hendel, Rene Antonio Vega, Sharvil A. Nanavati
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Patent number: 8694712Abstract: Various operations are disclosed for improving the operational efficiency of a virtual translation look-aside buffer (TLB) in a virtual machine environment. For example, operations are disclosed that allow for determination of whether present entries in shadow page tables (SPTs) are stale by comparing shadowed guest page table (GPT) entries against snapshots taken when the entries were cached. Other operations are disclosed that allow a virtual machine monitor (VMM) to access shadow page table trees (SPTTs) by walking trees in software or in hardware. Still other operations are disclosed allowing the VMM to use a hash table to relate GVA ranges to SPTs that map them, thus significantly reducing the cost of having to walk each SPTT in order to invalidate desired GVA(s). And, finally, operations are disclosed allowing the VMM to determine global GVA ranges by checking a bitmap, when invalidating global GVAs.Type: GrantFiled: December 5, 2006Date of Patent: April 8, 2014Assignee: Microsoft CorporationInventors: John Te-Jui Sheu, Matthew D. Hendel, Landy Wang, Ernest S. Cohen, Rene Antonio Vega, Sharvil A. Nanavati
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Patent number: 8615643Abstract: Various mechanisms are disclosed for improving the operational efficiency of a virtual translation look-aside buffer (TLB) in a virtual machine environment. For example, one mechanism fills in entries in a shadow page table (SPT) and additionally, speculatively fills in other entries in the SPT based on various heuristics. Another mechanism allows virtual TLBs (translation look-aside buffers) to cache partial walks in a guest page table tree. Still another mechanism allows for dynamic resizing of the virtual TLB to optimize for run-time characteristics of active workloads. Still another mechanism allows virtual machine monitors (VMMs) to support legacy and enlightened modes of virtual TLB operation. Finally, another mechanism allows the VMM to remove only the stale entries in SPTs when linking or switching address spaces. All these mechanisms, together or in part, increase the operational efficiency of the virtual TLB.Type: GrantFiled: December 5, 2006Date of Patent: December 24, 2013Assignee: Microsoft CorporationInventors: Ernest S. Cohen, John Te-Jui Sheu, Landy Wang, Matthew D. Hendel, Rene Antonio Vega, Sharvil A. Nanavati
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Patent number: 7788464Abstract: Various operations are provided that improve the scalability of virtual TLBs in multi-processor virtual machines, and they include: implicitly locking SPTs using per-processor generation counters; waiting for pending fills on other virtual processors to complete before servicing a GVA invalidation using the counters; write-protecting or unmaping guest pages in a deferred two-stage process or reclaiming SPTs in a deferred two-stage process; periodically coalescing two SPTs that shadow the same GPT with the same attributes; sharing SPTs between two SASes only at a specified level in a SPTT; flushing the entire virtual TLB using a generation counter; allocating a SPT to GPT from a NUMA node on which the GPT resides; having an instance for each NUMA node on which a virtual machine runs; and, correctly handling the serializing instructions executed by a guest in a virtual machine with more than one virtual processor sharing the virtual TLB.Type: GrantFiled: December 22, 2006Date of Patent: August 31, 2010Assignee: Microsoft CorporationInventors: John Te-Jui Sheu, Ernest S. Cohen, Matthew D. Hendel, Landy Wang, Rene Antonio Vega, Sharvil A. Nanavati
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Patent number: 7734837Abstract: The present invention relates to a system and methodology to facilitate I/O access to a computer storage medium in a predictable and efficient manner. A scheduling system is provided that mitigates the problem of providing differing levels of performance guarantees for disk I/O in view of varying levels of data access requirements. In one aspect, the scheduling system includes an algorithm or component that provides high performance I/O updates while maintaining high throughput to the disk in a bounded or determined manner. This is achieved by dynamically balancing considerations of I/O access time and latency with considerations of data scheduling requirements. Also, the system provides latency boundaries for multimedia applications as well as managing accesses for other applications.Type: GrantFiled: January 5, 2007Date of Patent: June 8, 2010Assignee: Microsoft CorporationInventors: Matthew D. Hendel, Fnu Sidhartha, Jane Win-Shih Liu
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Patent number: 7650482Abstract: Enhanced shadow page table algorithms are presented for enhancing typical page table algorithms. In a virtual machine environment, where an operating system may be running within a partition, the operating system maintains it's own guest page tables. These page tables are not the real page tables that map to the real physical memory. Instead, the memory is mapped by shadow page tables maintained by a virtualing program, such as a hypervisor, that virtualizes the partition containing the operating system. Enhanced shadow page table algorithms provide efficient ways to harmonize the shadow page tables and the guest page tables. Specifically, by using tagged translation lookaside buffers, batched shadow page table population, lazy flags, and cross-processor shoot downs, the algorithms make sure that changes in the guest pages tables are reflected in the shadow page tables.Type: GrantFiled: September 4, 2007Date of Patent: January 19, 2010Assignee: Microsoft CorporationInventors: Eric P. Traut, Matthew D. Hendel, Rene Antonio Vega
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Patent number: 7484073Abstract: Tagged translation lookaside buffer consistency is enabled in the presence of a hypervisor of a virtual machine computing environment, in which multiple processes of multiple logical processors of guests are hosted by a virtual machine monitor or hypervisor component. The virtual machine monitor or hypervisor component maintains tagged TLB data associated with the plurality of processes on behalf of each of the plurality of logical processors, thereby ensuring consistency of the tagged TLB data across all of the plurality of processes.Type: GrantFiled: July 12, 2006Date of Patent: January 27, 2009Assignee: Microsoft CorporationInventors: Ernest S. Cohen, Matthew D. Hendel
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Patent number: 7475183Abstract: Provided are optimizations to the memory virtualization model employed in a virtual machine environment. An opportunistic hypervisor page mapping process is used in order to utilize large memory pages in a virtual machine environment. Using these optimizations, physical memory is being virtualized for the virtual machine in a manner that allows the operating system (OS) running within the virtual machine to take real and full advantage of large physical memory pages.Type: GrantFiled: December 12, 2005Date of Patent: January 6, 2009Assignee: Microsoft CorporationInventors: Eric P. Traut, Idan Avraham, Matthew D. Hendel
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Patent number: 7434003Abstract: An operating system is described that is capable of ascertaining whether it is executing in a virtual machine environment and is further capable of modifying its behavior to operate more efficiently and provide optimal behavior in a virtual machine environment. An operating system is enlightened so that it is aware of VMMs or hypervisors, taking on behavior that is optimal to that environment. The VMM or hypervisor informs the operating system of the optimal behavior, and vice versa.Type: GrantFiled: November 15, 2005Date of Patent: October 7, 2008Assignee: Microsoft CorporationInventors: Adrian J. Oney, Bryan Mark Willman, Eric P. Traut, Forrest Curtis Foltz, John Te-Jui Sheu, Matthew D. Hendel, Rene Antonio Vega
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Patent number: 7398430Abstract: A system and method for self-diagnosing a likely cause of a system crash is disclosed. A mechanism within an operating system checks for the existence of a stop code at startup of the machine. The existence of the stop code indicates that the system crashed during the previous session, and the type of system crash. The mechanism may read the stop code and implement a self-diagnostic procedure that corresponds to that stop code. In this manner, the mechanism may automate many of the tasks normally performed by humans, such as a system administrator, to self-diagnose the likely cause of the crash. If the crash occurs again, the mechanism, through the tracking procedures automatically implemented, may identify and report to a system administrator the likely cause of the crash, e.g. the particular faulty driver or configuration error.Type: GrantFiled: October 12, 2006Date of Patent: July 8, 2008Assignee: Microsoft CorporationInventors: Landy Wang, Matthew D. Hendel
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Publication number: 20080155168Abstract: Various operations are provided that improve the scalability of virtual TLBs in multi-processor virtual machines, and they include: implicitly locking SPTs using per-processor generation counters; waiting for pending fills on other virtual processors to complete before servicing a GVA invalidation using the counters; write-protecting or unmaping guest pages in a deferred two-stage process or reclaiming SPTs in a deferred two-stage process; periodically coalescing two SPTs that shadow the same GPT with the same attributes; sharing SPTs between two SASes only at a specified level in a SPTT; flushing the entire virtual TLB using a generation counter; allocating a SPT to GPT from a NUMA node on which the GPT resides; having an instance for each NUMA node on which a virtual machine runs; and, correctly handling the serializing instructions executed by a guest in a virtual machine with more than one virtual processor sharing the virtual TLB.Type: ApplicationFiled: December 22, 2006Publication date: June 26, 2008Applicant: Microsoft CorporationInventors: John Te-Jui Sheu, Ernest S. Cohen, Matthew D. Hendel, Landy Wang, Rene Antonio Vega, Sharvil A. Nanavati
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Publication number: 20080134174Abstract: Various operations are disclosed for improving the operational efficiency of a virtual translation look-aside buffer (TLB) in a virtual machine environment. For example, operations are disclosed that allow for determination of whether present entries in shadow page tables (SPTs) are stale by comparing shadowed guest page table (GPT) entries against snapshots taken when the entries were cached. Other operations are disclosed that allow a virtual machine monitor (VMM) to access shadow page table trees (SPTTs) by walking trees in software or in hardware. Still other operations are disclosed allowing the VMM to use a hash table to relate GVA ranges to SPTs that map them, thus significantly reducing the cost of having to walk each SPTT in order to invalidate desired GVA(s). And, finally, operations are disclosed allowing the VMM to determine global GVA ranges by checking a bitmap, when invalidating global GVAs.Type: ApplicationFiled: December 5, 2006Publication date: June 5, 2008Applicant: Microsoft CorporationInventors: John Te-Jui Sheu, Matthew D. Hendel, Landy Wang, Ernest S. Cohen, Rene Antonio Vega, Sharvil A. Nanavati