Patents by Inventor Matthew Fernandez
Matthew Fernandez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11797309Abstract: An apparatus and method for tracking speculative execution flow and detecting potential vulnerabilities.Type: GrantFiled: December 27, 2019Date of Patent: October 24, 2023Assignee: Intel CorporationInventors: Carlos Rozas, Francis McKeen, Pasquale Cocchini, Meltem Ozsoy, Matthew Fernandez
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Publication number: 20220207148Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes decode circuitry and branch circuitry coupled to the decode circuitry. The decode circuitry is to decode a branch hardening instruction to mitigate vulnerability to a speculative execution attack. The branch circuitry is to be hardened in response to the branch hardening instruction.Type: ApplicationFiled: December 26, 2020Publication date: June 30, 2022Applicant: Intel CorporationInventors: Carlos Rozas, Fangfei Liu, Xiang Zou, Francis McKeen, Jason W. Brandt, Joseph Nuzman, Alaa Alameldeen, Abhishek Basak, Scott Constable, Thomas Unterluggauer, Asit Mallick, Matthew Fernandez
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Publication number: 20220207147Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes decode circuitry and execution circuitry coupled to the decode circuitry. The decode circuitry is to decode a register hardening instruction to mitigate vulnerability to a speculative execution attack. The execution circuitry is to be hardened in response to the register hardening instruction.Type: ApplicationFiled: December 26, 2020Publication date: June 30, 2022Applicant: Intel CorporationInventors: Carlos Rozas, Fangfei Liu, Xiang Zou, Francis McKeen, Jason W. Brandt, Joseph Nuzman, Alaa Alameldeen, Abhishek Basak, Scott Constable, Thomas Unterluggauer, Asit Mallick, Matthew Fernandez
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Publication number: 20220207146Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes decode circuitry and load circuitry coupled to the decode circuitry. The decode circuitry is to decode a load hardening instruction to mitigate vulnerability to a speculative execution attack. The load circuitry is to be hardened in response to the load hardening instruction.Type: ApplicationFiled: December 26, 2020Publication date: June 30, 2022Applicant: Intel CorporationInventors: Carlos Rozas, Fangfei Liu, Xiang Zou, Francis McKeen, Jason W. Brandt, Joseph Nuzman, Alaa Alameldeen, Abhishek Basak, Scott Constable, Thomas Unterluggauer, Asit Mallick, Matthew Fernandez
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Publication number: 20220206818Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes decode circuitry and execution circuitry coupled to the decode circuitry. The decode circuitry is to decode a single instruction to mitigate vulnerability to a speculative execution attack. The execution circuitry is to be hardened in response to the single instruction.Type: ApplicationFiled: December 26, 2020Publication date: June 30, 2022Applicant: Intel CorporationInventors: Alaa Alameldeen, Carlos Rozas, Fangfei Liu, Xiang Zou, Francis McKeen, Jason W. Brandt, Joseph Nuzman, Abhishek Basak, Scott Constable, Thomas Unterluggauer, Asit Mallick, Matthew Fernandez
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Publication number: 20220207138Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes a decode circuitry and store circuitry coupled to the decode circuitry. The decode circuitry is to decode a store hardening instruction to mitigate vulnerability to a speculative execution attack. The store circuitry is to be hardened in response to the store hardening instruction.Type: ApplicationFiled: December 26, 2020Publication date: June 30, 2022Applicant: Intel CorporationInventors: Carlos Rozas, Fangfei Liu, Xiang Zou, Francis McKeen, Jason W. Brandt, Joseph Nuzman, Alaa Alameldeen, Abhishek Basak, Scott Constable, Thomas Unterluggauer, Asit Mallick, Matthew Fernandez
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Publication number: 20220207154Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes a hybrid key generator and memory protection hardware. The hybrid key generator is to generate a hybrid key based on a public key and multiple process identifiers. Each of the process identifiers corresponds to one or more memory spaces in a memory. The memory protection hardware is to use the first hybrid key to protect to the memory spaces.Type: ApplicationFiled: December 26, 2020Publication date: June 30, 2022Applicant: Intel CorporationInventors: Richard Winterton, Mohammad Reza Haghighat, Asit Mallick, Alaa Alameldeen, Abhishek Basak, Jason W. Brandt, Michael Chynoweth, Carlos Rozas, Scott Constable, Martin Dixon, Matthew Fernandez, Fangfei Liu, Francis McKeen, Joseph Nuzman, Gilles Pokam, Thomas Unterluggauer, Xiang Zou
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Publication number: 20210200551Abstract: An apparatus and method for tracking speculative execution flow and detecting potential vulnerabilities.Type: ApplicationFiled: December 27, 2019Publication date: July 1, 2021Applicant: Intel CorporationInventors: CARLOS ROZAS, FRANCIS MCKEEN, PASQUALE COCCHINI, MELTEM OZSOY, MATTHEW FERNANDEZ
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Patent number: 10922088Abstract: Detailed herein are systems, apparatuses, and methods for a computer architecture with instruction set support to mitigate against page fault- and/or cache-based side-channel attacks. In an embodiment, an apparatus includes a decoder to decode a first instruction, the first instruction having a first field for a first opcode that indicates that execution circuitry is to set a first flag in a first register that indicates a mode of operation that redirects program flow to an exception handler upon the occurrence of an event. The apparatus further includes execution circuitry to execute the decoded first instruction to set the first flag in the first register that indicates the mode of operation and to store an address of an exception handler in a second register.Type: GrantFiled: June 29, 2018Date of Patent: February 16, 2021Assignee: Intel CorporationInventors: Fangfei Liu, Bin Xing, Michael Steiner, Mona Vij, Carlos Rozas, Francis McKeen, Meltem Ozsoy, Matthew Fernandez, Krystof Zmudzinski, Mark Shanahan
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PROCESSOR INSTRUCTION SUPPORT FOR MITIGATING CONTROLLED-CHANNEL AND CACHE-BASED SIDE-CHANNEL ATTACKS
Publication number: 20200409711Abstract: Detailed herein are systems, apparatuses, and methods for a computer architecture with instruction set support to mitigate against page fault and/or cache-based side-channel attacks. In an embodiment, a processor includes a decoder to decode an instruction into a decoded instruction, the instruction comprising a first field that indicates an instruction pointer to a user-level event handler; and an execution unit to execute the decoded instruction to, after a swap of an instruction pointer that indicates where an event occurred from a current instruction pointer register into a user-level event handler pointer register, push the instruction pointer that indicates where the event occurred onto call stack storage, and change a current instruction pointer in the current instruction pointer register to the instruction pointer to the user-level event handler.Type: ApplicationFiled: June 29, 2019Publication date: December 31, 2020Inventors: Scott Constable, Fangfei Liu, Bin Xing, Michael Steiner, Mona Vij, Carlos Rozas, Francis X. McKeen, Meltem Ozsoy, Matthew Fernandez, Krystof Zmudzinski, Mark Shanahan -
Publication number: 20200004552Abstract: Detailed herein are systems, apparatuses, and methods for a computer architecture with instruction set support to mitigate against page fault- and/or cache-based side-channel attacks. In an embodiment, an apparatus includes a decoder to decode a first instruction, the first instruction having a first field for a first opcode that indicates that execution circuitry is to set a first flag in a first register that indicates a mode of operation that redirects program flow to an exception handler upon the occurrence of an event. The apparatus further includes execution circuitry to execute the decoded first instruction to set the first flag in the first register that indicates the mode of operation and to store an address of an exception handler in a second register.Type: ApplicationFiled: June 29, 2018Publication date: January 2, 2020Inventors: Fangfei LIU, Bin XING, Michael STEINER, Mona VIJ, Carlos ROZAS, Francis MCKEEN, Meltem OZSOY, Matthew FERNANDEZ, Krystof ZMUDZINSKI, Mark SHANAHAN
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Patent number: 9549068Abstract: A method for adaptive voice interaction includes monitoring voice communications between a service recipient and a service representative, measuring a set of voice communication features based upon the voice communications between the service recipient and the service representative, analyzing the set of voice communication features to generate emotion metric values, and generating a response based on the analysis of the set of voice communication features.Type: GrantFiled: January 28, 2015Date of Patent: January 17, 2017Assignee: Simple Emotion, Inc.Inventors: Akash Krishnan, Matthew Fernandez
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Publication number: 20150213800Abstract: A method for adaptive voice interaction includes monitoring voice communications between a service recipient and a service representative, measuring a set of features based upon the voice communications, and analyzing the set of features to generate emotion metric values.Type: ApplicationFiled: January 28, 2015Publication date: July 30, 2015Inventors: Akash Krishnan, Matthew Fernandez
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Patent number: 8825479Abstract: A computerized method, software, and system for recognizing emotions from a speech signal, wherein statistical and MFCC features are extracted from the speech signal, the MFCC features are sorted to provide a basis for comparison between the speech signal and reference samples, the statistical and MFCC features are compared between the speech signal and reference samples, a scoring system is used to compare relative correlation to different emotions, a probable emotional state is assigned to the speech signal based on the scoring system and the probable emotional state is communicated to a user.Type: GrantFiled: October 24, 2013Date of Patent: September 2, 2014Assignee: Simple Emotion, Inc.Inventors: Akash Krishnan, Matthew Fernandez
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Publication number: 20140052448Abstract: A computerized method, software, and system for recognizing emotions from a speech signal, wherein statistical and MFCC features are extracted from the speech signal, the MFCC features are sorted to provide a basis for comparison between the speech signal and reference samples, the statistical and MFCC features are compared between the speech signal and reference samples, a scoring system is used to compare relative correlation to different emotions, a probable emotional state is assigned to the speech signal based on the scoring system and the probable emotional state is communicated to a user.Type: ApplicationFiled: October 24, 2013Publication date: February 20, 2014Applicant: Simple Emotion, Inc.Inventors: Akash Krishnan, Matthew Fernandez
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Patent number: 8595005Abstract: A computerized method, software, and system for recognizing emotions from a speech signal, wherein statistical and MFCC features are extracted from the speech signal, the MFCC features are sorted to provide a basis for comparison between the speech signal and reference samples, the statistical and MFCC features are compared between the speech signal and reference samples, a scoring system is used to compare relative correlation to different emotions, a probable emotional state is assigned to the speech signal based on the scoring system, and the probable emotional state is communicated to a user.Type: GrantFiled: April 22, 2011Date of Patent: November 26, 2013Assignee: Simple Emotion, Inc.Inventors: Akash Krishnan, Matthew Fernandez
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Publication number: 20110295607Abstract: A computerized method, software, and system for recognizing emotions from a speech signal, wherein statistical and MFCC features are extracted from the speech signal, the MFCC features are sorted to provide a basis for comparison between the speech signal and reference samples, the statistical and MFCC features are compared between the speech signal and reference samples, a scoring system is used to compare relative correlation to different emotions, a probable emotional state is assigned to the speech signal based on the scoring system, and the probable emotional state is communicated to a user.Type: ApplicationFiled: April 22, 2011Publication date: December 1, 2011Inventors: Akash Krishnan, Matthew Fernandez