Abstract: A single data bus to a memory device can be split up into a number of data bus portions, each of which is managed by a different respective controller chip of multiple controller chips. During a memory access to a respective memory device, each of the multiple controller chips controls a different corresponding portion of the data bus to retrieve data from or store data to the memory device depending on whether the access is a read or write. To perform the data access, a synchronizer circuit (internal and/or external to the memory controller chips) synchronizes the multiple memory controller chips such that one of the memory controller chips drives the address bus and/or control signals to the memory device. After setting the address to the memory device, the memory controller chips either read data from or write data to the memory device based on the address.

Abstract: A single data bus to a memory device can be split up into a number of data bus portions, each of which is managed by a different respective controller chip of multiple controller chips. During a memory access to a respective memory device, each of the multiple controller chips controls a different corresponding portion of the data bus to retrieve data from or store data to the memory device depending on whether the access is a read or write. To perform the data access, a synchronizer circuit (internal and/or external to the memory controller chips) synchronizes the multiple memory controller chips such that one of the memory controller chips drives the address bus and/or control signals to the memory device. After setting the address to the memory device, the memory controller chips either read data from or write data to the memory device based on the address.

Abstract: An on-demand server system herein includes a memory controller that coordinates access to one or more flash-based memory devices. The flash devices store large amounts of video content that can be selectively viewed on-demand by each of multiple destinations over a respective network. In addition to having access to an array of flash memory devices, the memory controller has access to a corresponding read buffer and write buffer. Use of the read buffer and the write buffer enable the memory controller to switch between transferring data stored in the write buffer to the array of memory devices and transferring the data in the array of memory devices to the read buffer. The write buffer stores on-demand video content that can be selected for viewing by different users. The read buffer stores segments of the on-demand video content currently streamed to the users.

Abstract: A power line communication system. The system includes at least one transmitter for generating and transmitting signals over a power line and at least one receiver for the receipt of signals transmitted over the power line. The transmitter and receiver(s) devices include a storing mechanism containing the address of the device and a programming port for electrical connection to a mating connector of a programmer. The programmer also includes a selector for selection of a desired address such that the address of the addressable device may be changed by the programmer. The transmitter also includes a timing mechanism for automatically retransmitting signals over the power line and the receiver includes a time measuring mechanism for ascertaining whether a signal has been received within a predetermined time period and a mechanism for setting the receiver in a default state should no signals be received within that time period.